NP50P06KDG Просмотр технического описания (PDF) - NEC => Renesas Technology
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NP50P06KDG Datasheet PDF : 7 Pages
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NP50P06KDG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS
Gate Leakage Current
IGSS
Gate to Source Threshold Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
VGS(th)
| yfs |
RDS(on)1
RDS(on)2
Input Capacitance
Ciss
VDS = −60 V, VGS = 0 V
VGS = m20 V, VDS = 0 V
VDS = −10 V, ID = −1 mA
VDS = −10 V, ID = −25 A
VGS = −10 V, ID = −25 A
VGS = −4.5 V, ID = −25 A
VDS = −10 V,
Output Capacitance
Coss
VGS = 0 V,
Reverse Transfer Capacitance
Turn-on Delay Time
Crss
td(on)
f = 1 MHz
VDD = −30 V, ID = −25 A,
Rise Time
tr
VGS = −10 V,
Turn-off Delay Time
td(off)
RG = 0 Ω
Fall Time
Total Gate Charge
tf
QG
VDD = −48 V,
Gate to Source Charge
QGS
VGS = −10 V,
Gate to Drain Charge
Body Diode Forward Voltage Note
Reverse Recovery Time
Reverse Recovery Charge
QGD
VF(S-D)
trr
Qrr
ID = −50 A
IF = −50 A, VGS = 0 V
IF = −50 A, VGS = 0 V,
di/dt = −100 A/μs
Note Pulsed test PW ≤ 350 μs, Duty Cycle ≤ 2%
MIN.
−1.0
15
TYP.
−1.6
30
13.5
15.4
5000
600
300
20
45
405
270
95
10
26
0.97
50
70
MAX.
−10
m100
−2.5
17
23
1.5
UNIT
μA
nA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = −20 → 0 V
−
IAS BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS(−)
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS(−)
VGS
Wave Form
0 10%
VDS(−)
90%
VDS
VDS
Wave Form 0
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = −2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet D18689EJ3V0DS
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