HI5746KCBZ-T Просмотр технического описания (PDF) - Intersil

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HI5746KCBZ-T

10-Bit, 40MSPS A/D Converter

Intersil 

HI5746

φ1

VIN+ φ1

φ2

VIN-

φ1

CS

CS

φ1

CH

-+

+-

CH

φ1

VOUT+

VOUT-

φ1

FIGURE 25. ANALOG INPUT SAMPLE-AND-HOLD

As illustrated in the functional block diagram and the timing

diagram in Figure 1, eight identical pipeline subconverter

stages, each containing a two-bit flash converter and a

two-bit multiplying digital-to-analog converter, follow the S/H

circuit with the ninth stage being a two bit flash converter.

Each converter stage in the pipeline will be sampling in one

phase and amplifying in the other clock phase. Each

individual subconverter clock signal is offset by 180 degrees

from the previous stage clock signal resulting in alternate

stages in the pipeline performing the same operation.

The output of each of the eight identical two-bit subconverter

stages is a two-bit digital word containing a supplementary bit

to be used by the digital error correction logic. The output of

each subconverter stage is input to a digital delay line which is

controlled by the internal sampling clock. The function of the

digital delay line is to time align the digital outputs of the eight

identical two-bit subconverter stages with the corresponding

output of the ninth stage flash converter before applying the

eighteen bit result to the digital error correction logic. The

digital error correction logic uses the supplementary bits to

correct any error that may exist before generating the final ten

bit digital data output of the converter.

Because of the pipeline nature of this converter, the digital

data representing an analog input sample is output to the

digital data bus on the 7th cycle of the clock after the analog

sample is taken. This time delay is specified as the data

latency. After the data latency time, the digital data

representing each succeeding analog sample is output

during the following clock cycle. The digital output data is

synchronized to the external sampling clock by a double

buffered latching technique. The output of the digital error

correction circuit is available in two’s complement or offset

binary format depending on the state of the Data Format

Select (DFS) control input (see Table 1, A/D Code Table).

Reference Voltage Inputs, VREF - and VREF+

The HI5746 is designed to accept two external reference

voltage sources at the VREF input pins. Typical operation of

the converter requires VREF+ to be set at +2.5V and VREF- to

be set at 2.0V. However, it should be noted that the input

structure of the VREF+ and VREF- input pins consists of a

resistive voltage divider with one resistor of the divider

(nominally 500Ω) connected between VREF+ and VREF- and

the other resistor of the divider (nominally 2000Ω) connected

between VREF- and analog ground. This allows the user the

option of supplying only the +2.5V VREF+ voltage reference

with the +2.0V VREF- being generated internally by the

voltage division action of the input structure.

The HI5746 is tested with VREF- equal to +2.0V and VREF+

equal to +2.5V yielding a fully differential analog input voltage

range of ±0.5V. VREF+ and VREF- can differ from the above

voltages (see the Typical Performance Curves, Figure 8

through Figure 13).

In order to minimize overall converter noise it is recommended

that adequate high frequency decoupling be provided at both

of the reference voltage input pins, VREF+ and VREF-.

Analog Input, Differential Connection

The analog input to the HI5746 is a differential input that can

be configured in various ways depending on the signal

source and the required level of performance. A fully

differential connection (Figure 26 and Figure 27) will give the

best performance for the converter.

VIN

-VIN

VIN+

R

HI5746

VDC

R

VIN-

FIGURE 26. AC COUPLED DIFFERENTIAL INPUT

Since the HI5746 is powered by a single +5V analog supply,

the analog input is limited to be between ground and +5V.

For the differential input connection this implies the analog

input common mode voltage can range from 0.25V to 4.75V.

The performance of the ADC does not change significantly

with the value of the analog input common mode voltage.

A DC voltage source, VDC, equal to 3.2V (typical), is made

available to the user to help simplify circuit design when using

an AC coupled differential input. This low output impedance

voltage source is not designed to be a reference but makes an

excellent DC bias source and stays well within the analog

input common mode voltage range over temperature (see the

Typical Performance Curves, Figure 21).

For the AC coupled differential input (Figure 26) assume

the difference between VREF+, typically 2.5V, and VREF-,

typically 2.0V, is 0.5V. Full scale is achieved when the VIN

and -VIN input signals are 0.5VP-P, with -VIN being

180 degrees out of phase with VIN. The converter will be

12

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