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NLSX5012DMR2G

2-Bit 100 Mb/s Configurable Dual-Supply Level Translator

ON Semiconductor 

NLSX5012

IMPORTANT APPLICATIONS INFORMATION

Level Translator Architecture

The NLSX5012 auto−sense translator provides

bi−directional logic voltage level shifting to transfer data

in multiple supply voltage systems. These level translators

have two supply voltages, VL and VCC, which set the logic

levels on the input and output sides of the translator. When

used to transfer data from the I/O VL to the I/O VCC ports,

input signals referenced to the VL supply are translated to

output signals with a logic level matched to VCC. In a

similar manner, the I/O VCC to I/O VL translation shifts

input signals with a logic level compatible to VCC to an

output signal matched to VL.

The NLSX5012 translator consists of bi−directional

channels that independently determine the direction of the

data flow without requiring a directional pin. One−shot

circuits are used to detect the rising or falling input signals.

In addition, the one−shots decrease the rise and fall times

of the output signal for high−to−low and low−to−high

transitions.

Input Driver Requirements

Auto−sense translators such as the NLSX5012 have a

wide bandwidth, but a relatively small DC output current

rating. The high bandwidth of the bi−directional I/O circuit

is used to quickly transform from an input to an output

driver and vice versa. The I/O ports have a modest DC

current output specification so that the output driver can be

over driven when data is sent in the opposite direction. For

proper operation, the input driver to the auto−sense

translator should be capable of driving 2 mA of peak output

current. The bi−directional configuration of the translator

results in both input stages being active for a very short time

period. Although the peak current from the input signal

circuit is relatively large, the average current is small and

consistent with a standard CMOS input stage.

Enable Input (EN)

The NLSX5012 translator has an Enable pin (EN) that

provides tri−state operation at the I/O pins. Driving the

Enable pin to a low logic level minimizes the power

consumption of the device and drives the I/O VCC and I/O

VL pins to a high impedance state. Normal translation

operation occurs when the EN pin is equal to a logic high

signal. The EN pin is referenced to the VL supply and has

Over−Voltage Tolerant (OVT) protection.

Uni−Directional versus Bi−Directional Translation

The NLSX5012 translator can function as a

non−inverting uni−directional translator. One advantage of

using the translator as a uni−directional device is that each

I/O pin can be configured as either an input or output. The

configurable input or output feature is especially useful in

applications such as SPI that use multiple uni−directional

I/O lines to send data to and from a device. The flexible I/O

port of the auto sense translator simplifies the trace

connections on the PCB.

Power Supply Guidelines

The values of the VL and VCC supplies can be set to

anywhere between 0.9 and 4.5 V. Design flexibility is

maximized because VL may be either greater than or less

than the VCC supply. In contrast, the majority of the

competitive auto sense translators has a restriction that the

value of the VL supply must be equal to less than (VCC −

0.4) V.

The sequencing of the power supplies will not damage

the device during power−up operation. In addition, the I/O

VCC and I/O VL pins are in the high impedance state if

either supply voltage is equal to 0 V. For optimal

performance, 0.01 to 0.1 mF decoupling capacitors should

be used on the VL and VCC power supply pins. Ceramic

capacitors are a good design choice to filter and bypass any

noise signals on the voltage lines to the ground plane of the

PCB. The noise immunity will be maximized by placing

the capacitors as close as possible to the supply and ground

pins, along with minimizing the PCB connection traces.

The NLSX5012 translators have a power down feature

that provides design flexibility. The output ports are

disabled when either power supply is off (VL or VCC = 0 V).

This feature causes all of the I/O pins to be in the power

saving high impedance state.

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