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NJW4351 Просмотр технического описания (PDF) - Japan Radio Corporation

Номер в каталоге
Компоненты Описание
производитель
NJW4351
JRC
Japan Radio Corporation  JRC
NJW4351 Datasheet PDF : 18 Pages
First Prev 11 12 13 14 15 16 17 18
NJW4351
POR – Power On And Reset Function
The POR connected to VDD is to prevent miss-step under unstable condition of the inputting of logic supply
voltage VDD.
After inputting VDD, the phase outputs are set to the initial energizing pattern output status.
PHASE OUTPUT BLOCK
The phase output block consists of four open-drain DMOS FET capable of sinking max 1.5A.
MO – Motor Origin Monitor
In initialized position of the Translator, MO output low to indicate to external devices that it is the initial energizing
pattern output status.
- 12 -
Ver.2010-03-26

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