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HI5710A

10-Bit, 20 MSPS A/D Converter

Intersil 

HI5710A

Detailed Description

The HI5710A is a two step A/D converter featuring a 5-bit

upper comparator group and a 5-bit lower comparator group.

A user controllable internal calibration unit is used to improve

linearity.

The voltage references must be supplied externally, with VRB

and VRT typically being set to 2.0V and 4.0V respectively.

Both chip enable and output enable pins are provided for

flexibility and to reduce power consumption. The digital

outputs can be inverted by control inputs LINV and MINV,

where LINV controls outputs D0 through D8 and MINV con-

trols output D9 (MSB). This allows for various digital output

data formats, such as straight binary, inverted binary, offset

two’s complement or inverted offset two’s complement.

Analog Input

The analog input typically requires a 2VP-P full scale input

signal. The full scale input can range from 1.8VP-P to

2.8VP-P dependent on the voltage references used.

The input capacitance is small when compared with other flash

type A/D converters. However, it is necessary to drive the input

with an amplifier with sufficient bandwidth and drive capability.

Op amps such as the HA5020 should make an excellent input

amplifier depending on the application requirements. In order to

prevent parasitic oscillation, it may be necessary to insert a

resistor between the output of the amplifier and the A/D input.

Be sure to consider the amplifiers settling time in CCD

applications or where step inputs are expected.

Reference Input

The analog input voltage range of the A/D is set by the voltage

difference between the VRT and VRB voltage references. The

HI5710A is designed for use with external voltage references

of 2.0V and 4.0V on VRB and VRT, respectively. The analog

input voltage range of the A/D will now be from 2.0V to 4.0V.

The VRB voltage reference range is 1.8V to 2.8V and the VRT

voltage reference range is 3.6V to 4.6V. The voltage

difference between the VRT and VRB voltage references,

(VRT - VRB), can range from 1.8V to 2.8V.

The VRT and VRB voltage reference input pins must be

decoupled to analog ground to minimize noise on these

references. A 0.1µF capacitor is usually adequate.

Clock Input

The HI5710A samples the input signal on the rising edge of the

clock with the digital data being latched at the digital outputs

(D0 - D9) after 3 clock cycles. The HI5710A is designed for use

with a 50% duty cycle square wave, but a 10% variation should

not affect performance.

The clock input can be driven from +3.3V CMOS or +5V

TTL/CMOS logic. When using a +3.3V digital supply, HC or

AC CMOS logic will work well.

Digital Inputs

The digital inputs can be driven from +3.3V CMOS or +5V

TTL/CMOS logic. When using a +3.3V digital supply, HC or

AC CMOS logic will work well.

Digital Outputs

The digital outputs are CMOS outputs. The LINV control

input will invert outputs D0 through D8 and MINV control

input will invert output D9 (MSB). This allows the user to set

the digital output data for a number of different digital for-

mats. The outputs can also be three-stated by pulling the OE

control input high.

The digital output supply can run from +3.3V or +5V. The

digital outputs will generate less radiated noise using +3.3V,

but the outputs will have less drive capability. The digital

outputs will only swing to DVDD, therefore exercise care if

interfacing to +5V logic when using a +3.3V supply.

The digital output data can also be set to a fixed,

predetermined state, through the use of the TESTMODE,

LINV and MINV control input signals, see the Digital Output

Data Format table. By setting the TESTMODE pin low, the

outputs go to a defined digital pattern. This pattern is varied

by the MINV and LINV control inputs. This feature can be

used for in-circuit testing of the digital output data bus.

Calibration Function

The HI5710A has a built-in calibration unit which is designed

to provide superior linearity by correcting the gain error of

the subrange amplification circuitry. In addition to the

calibration unit, the HI5710A provides a built-in auto

calibration pulse generation function. Figure 20 shows a

functional block diagram of the auto calibration pulse

generator circuit.

The calibration pulse generation functions provided can be

subdivided into four operational areas. The first function is

the generation of the calibration pulses required to complete

the initial (power-up) calibration process when power is first

supplied to the converter. The next two functions accommo-

dated are the generation of periodic calibration pulses, either

internally or externally, to maintain calibration. The last

function is the provision for externally initiating or re-initiating

the power-up calibration process.

Power-up Calibration Function

The initial power-up calibration requires over 600 calibration

pulses in order to complete the calibration process when

power is first applied to the converter. The power-up calibra-

tion function provided by the auto calibration pulse generator

automatically generates these pulses internally and

completes the initial calibration process. The following five

conditions must be satisfied in order for the auto calibration

pulse generator power-up calibration process to be initiated :

a) The voltage between AVDD and AVSS is approximately

2.5V or more.

b) The voltage between VRT and VRB is approximately 1.0V

or more.

c) The RESET control input pin (Pin 15) must be high

(logic 1).

d) The CE control input pin (Pin 24) must be low (logic 0).

e) Condition b must be met after condition a.

Once all five of these conditions is satisfied the power-up

calibration pulses are generated. These power-up calibration

pulses are derived from a divided-by sixteen sample clock

4-1542

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