NCV70501DW002G Просмотр технического описания (PDF) - ON Semiconductor
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NCV70501DW002G Datasheet PDF : 22 Pages
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NCV70501
Table 8. SPI TIMING PARAMETERS
Symbol
Parameter
Min
Typ
Max Unit
tCLK
SPI clock period
1
tHI_CLK
SPI clock high time
200
tCLKRISE
SPI clock rise time
tCLKFALL
SPI clock fall time
tLO_CLK
SPI clock low time
200
tSET_DI
DI set up time, valid data before rising edge of CLK
50
tHOLD_DI
DI hold time, hold data after rising edge of CLK
50
tHI_CSB
CSB high time
2.5
tSET_CSB_LO CSB set up time, CSB low before rising edge of CLK (Note 13)
1
tCLK_CSB_HI CSB set up time, CSB high after rising edge of CLK
200
tDEL_CSB_DO DO delay time, DO settling time after CSB low (Note 14)
tDEL_CLK_DO DO delay time, DO settling time after CLK low (Note 14)
13. After leaving sleep mode an additional wait time of 250 ms is needed before pulling CSB low.
14. Specified for a capacitive load 10 pF and a pullup resistor of 1.5 kW.
ms
ns
1
ms
1
ms
ns
ns
ns
ms
ms
ns
250
ns
100
ns
0.8VCC
CS
0.2VCC
t HI_CSB
t SET_CSB_LO
tCLK
tCLKRISE
t CLKFALL
CLK
0.8VCC
0.2VCC
tHI_CLK
tLO _ CLK
tSET_DI
tHOLD _DI
0.8VCC
ÏÏÏÏÏÏÏÏÏÏÏÏ DI
Valid
Valid
TCLK_CSB _HI
Valid ÏÏÏÏÏÏÏÏÏÏ
tDEL_CSB _DO
ÏÏÏÏÏ 0.8VCC
DO
ÏÏÏÏÏÏÏÏÏÏ Valid
tDEL_CLK_DO
Valid
Figure 3. SPI Timing
Valid
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
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