NCP1236 Просмотр технического описания (PDF) - ON Semiconductor

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NCP1236

Fixed Frequency Current Mode Controller for Flyback Converters

ON Semiconductor 

NCP1236

IP

ILIMIT

High

Line

IP to be

compensated

Low

Line

tdelay

tdelay

time

Figure 38. Line Compensation for True Overpower Protection

To compensate this and have an accurate overpower

protection, an offset proportional to the input voltage is

added on the CS signal by turning on an internal current

source: by adding an external resistor in series between the

sense resistor and the CS pin, a voltage offset is created

across it by the current. The compensation can be adjusted

by changing the value of the resistor.

But this offset is unwanted to appear when the current

sense signal is small, i.e. in light load conditions, where it

would be in the same order of magnitude. Therefore the

compensation current is only added when the FB voltage is

higher than VFB(OPCE).

However, because the HV pin can be connected to an ac

voltage, there is needed an additional circuitry to read or at

least closely estimate the actual voltage on the bulk

capacitor.

HV

VHVstop

(68 ms)

HV Timer

thv

SQ

R Q Brown Out

(32 ms)

Watch

Dog

A/D 3 bit

Converter

+

Peak Detector

3 bit

Register

I Generator

I ctrl

FB

VFB (OPC)

To CS

Block

Tblanking

LEB

CS

Figure 39. Schematic Overpower Compensation Circuit

A 3 bit A/D converter with the peak detector senses the ac

input, and its output is periodically sampled and reset, in

order to follow closely the input voltage variations. The

sample and reset events are given by the VHV(stop)

comparator used for sampling detection for the AC line

input. If only the DC high voltage input is used, no reset

signal is generated by the VHV(stop) condition and the 32 ms

watch dog is used to generate the sampling events for

sampling the DC input high voltage line.

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