NCP1218 Просмотр технического описания (PDF) - ON Semiconductor

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NCP1218

PWM Controller with Adjustable Skip Level and External Latch Input

ON Semiconductor 

NCP1218

Oscillator Frequency

11.5 ms

fOSC + 11%

fOSC

fOSC − 11%

time

Figure 34. Oscillator Frequency Modulation

Gate Drive

The output drive of the NCP1218 is designed to directly

drive the gate of an n−channel power MOSFET. The DRV

pin is capable of sourcing 500 mA and sinking 800 mA of

drive current. It has typical rise and fall times of 30 ns and

20 ns, respectively, driving a 1 nF capacitive load.

The power dissipation of the output stage while driving

the capacitance of the power MOSFET must be considered

when calculating the NCP1218 power dissipation. The

driver power dissipation can be calculated using

Equation 8,

PDRV + fOSC @ QG @ VCC

(eq. 8)

where QG is the gate charge of the power MOSFET.

External Latch Input

Board level protection functionality is often

incorporated using external circuits to suit a specific

application. An external fault condition can be used to

disable the controller by bringing the voltage on the

Skip/latch pin above the latch threshold, Vlatch (3.9 V

typical). When an external fault condition is detected, the

DRV signal is stopped, and the controller enters low current

operation mode. The external capacitor CCC discharges

and VCC drops until VCC(hiccup) is reached. The high

voltage startup circuit turns on and Istart charges CCC until

VCC(on) is reached. VCC cycles between VCC(on) and

VCC(hiccup) until VCC reaches VCC(reset). Voltage must be

removed from the HV pin, disabling the startup current and

allowing CCC to discharge to VCC(reset). Therefore, the

controller is reset by unplugging the power supply from the

wall to allow Vbulk to discharge. Figure 35 illustrates the

timing diagram of VCC in the latch−off condition.

Startup current source is

charging the VCCcapacitor

VCC(on)

Startup current source is

off when V CC is VCC(on)

VCC(hiccup)

Startup current source turns

on when VCC reaches VCC(hiccup)

time

Figure 35. Latch−off VCC Timing Diagram

The external latch feature allows the circuit designers to

implement different kinds of latching protection. Figure 36

shows an example circuit in which a bipolar transistor is

used to pull the Skip/latch pin above the latch threshold.

The RLIM value is chosen to prevent the Skip/latch pin from

exceeding the maximum rated voltage. The NCP1219

applications note (AND8393/D) details several simple

circuits to implement overtemperature protection (OTP)

and overvoltage protection (OVP).

VCC

RLIM

Fault

output

Cskip Rskip

Skip/latch HV

FB

CS

VCC

GND DRV

NCP1218

Figure 36. Circuit Example of an External

Latch−off Circuit

An internal blanking filter prevents fast voltage spikes

caused by noise from latching the part. However, it is

recommended that an external filter capacitor be placed as

close as possible to the Skip/latch pin to further improve the

noise immunity.

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