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NCP1218

PWM Controller with Adjustable Skip Level and External Latch Input

ON Semiconductor 

NCP1218

Ramp Compensation

Ramp compensation is a known mean to cure

subharmonic oscillations. These oscillations take place at

half the switching frequency and occur only during

continuous conduction mode (CCM) with a duty ratio

greater than 50%. To lower the current loop gain, one

usually injects 50 to 75% of the inductor current down

slope. The NCP1218 generates an internal current ramp

that is synchronized with the clock. This current ramp is

then routed to the CS pin. Figures 32 and 33 depict how the

ramp is generated and utilized. Ramp compensation is

simply formed by placing a resistor, Rramp, between the CS

pin and the sense resistor.

Ramp current, Iramp

Iramp(peak)

0

time

80% of period

100% of period

Figure 32. Internal Ramp Compensation Current

Source

DRV

Clock

Current

Ramp

Oscillator

Iramp(peak)

CS

Rramp

RCS

Figure 33. Inserting a Resistor in Series with the

Current Sense Information Provides Ramp

Compensation

In order to calculate the value of the ramp compensation

resistor, Rramp, the off time primary current slope,

Soff,primary must be calculated using Equation 4,

ǒ Ǔ (Vout ) Vf) @

Soff,primary +

LP

NP

NS

(eq. 4)

where Vout is the converter output voltage, Vf is the forward

diode drop of the secondary diode, NP/NS is the primary to

secondary turns ratio, and LP is the primary inductance of

the transformer. The value of Rramp can be calculated using

Equation 5,

ǒ Ǔ Soff,primary RCS @ %slope

Rramp +

ǒ Ǔ Iramp(peak) fOSC

D

(eq. 5)

where RCS is the current sense resistor and %slope is the

percentage of the current downslope to be used for ramp

compensation.

The NCP1218 has a peak ramp compensation current of

100 mA. A frequency of 65 kHz with an 80% maximum

duty ratio corresponds to an 8.1 mA/ms ramp. For a typical

flyback design, let’s assume that the primary inductance is

350 mH, the converter output is 19 V, the Vf of the output

diode is 1 V and the NP:NS ratio is 10:1. The off time

primary current slope is given by Equation 6.

ǒ Ǔ (Vout ) Vf)

NP

NS

LP

+

571

mA

ms

(eq. 6)

When projected over an RCS of 0.1 W (for example), this

becomes 57 mV/ms. If we select 50% of the downslope as

the required amount of ramp compensation, then we shall

inject 28.5 mV/ms. Therefore, Rramp is simply equal to

Equation 7.

Rramp

+

28.5

mV

ms

8.1

mA

ms

+

3.5

kW

(eq. 7)

Ramp compensation greater than 50% of the inductor

down slope can be used if necessary; however,

overcompensating will degrade the transient response of

the system. The addition of ramp compensation also

reduces the total available output power of the system.

Internal Oscillator

The internal oscillator of the NCP1218 provides the

clock signal that sets the DRV signal high and limits the

duty ratio to 80% (typical). The oscillator has a fixed

frequency of 65 kHz. The NCP1218 employs frequency

jittering to smooth the EMI signature of the system by

spreading the energy of the main switching component

across a range of frequencies. An internal low frequency

oscillator continuously varies the switching frequency of

the controller by ±11%. The period of modulation is

11.5 ms, typical. Figure 34 illustrates the oscillator

frequency modulation.

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