NCP1218 Просмотр технического описания (PDF) - ON Semiconductor

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NCP1218

PWM Controller with Adjustable Skip Level and External Latch Input

ON Semiconductor 

Soft−start voltage, VSSTART

NCP1218

1V

Iramp(peak) Iramp

Vbulk

time

tSSTART

Feedback pin voltage divided by 3, VFB/3

1V

time must be less than tOVLD

to prevent fault condition

Pulse Width Modulation voltage, VPWM

1V

tSSTART

Drain Current, ID

time

time

PWM

Output

Q

R

180 ns VCS

LEB

80% S

max duty

VPWM

(1 V max. signal)

Clock

CS

ID

RCS

Figure 30. Current−Mode Implementation

Figure 31 shows the timing diagram for the

current−mode pulse width modulation operation. An

internal clock sets the output RS latch, pulling the DRV pin

high. The latch is then reset when the voltage on the CS pin

intersects the modulation voltage, VPWM. This generates

the duty ratio of the DRV pulse. The maximum duty ratio

is internally limited to 80% (typical) by the output RS latch.

PWM

Output

VPWM

tSSTART

time

Figure 29. Soft−Start (Time = 0 at VCC = VCC(on))

Current−Mode Pulse Width Modulation

The NCP1218 is a current−mode, fixed frequency pulse

width modulation controller with ramp compensation. The

PWM block of the NCP1218 is shown in Figure 30. The

DRV signal is enabled by a clock pulse. At this time,

current begins to flow in the power MOSFET and the sense

resistor. A corresponding voltage is generated on the CS

pin of the device, ranging from very low to as high as the

maximum modulation voltage, VPWM (maximum of 1 V).

This sets the primary current on a cycle−by−cycle basis.

Equation 3 gives the maximum drain current, ID(MAX),

where RCS is the current sense resistor value and VILIM is

the current sense voltage threshold.

ID(MAX)

+

VILIM

RCS

(eq. 3)

VCS

clock

Figure 31. Current−Mode Timing Diagram

The VPWM voltage is the scaled representation of the FB

pin voltage. The scale factor, Iratio, is 3. The FB pin voltage

is provided by an external error amplifier, whose output is

a function of the power supply output. An FB signal

between Vskip and 3 V determines the duty ratio of the

controller output. The FB voltage operates in a closed loop

with the output voltage to regulate the power supply.

It is recommended that an external filter capacitor be

placed as close to the FB pin as possible to improve the

noise immunity.

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