NCP1218 Просмотр технического описания (PDF) - ON Semiconductor

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NCP1218

PWM Controller with Adjustable Skip Level and External Latch Input

ON Semiconductor 

VCC(on)

NCP1218

VCC(MIN)

UVLO

VCC(hiccup)

VCC(reset)

Fault2

Fault

DRV

ON

OFF

ON

Figure 26. VCC Double Hiccup Operation with a Fault Occurring While the Startup Circuit is Enabled

An internal supervisory circuit monitors the VCC voltage

to prevent the controller from dissipating excessive power

if the VCC pin is accidentally grounded. A lower level

current source (Iinhibit) charges CCC from 0 V to Vinhibit,

typically 0.67 V. Once VCC exceeds Vinhibit, the startup

current source is enabled. This behavior is illustrated in

Figure 27. This slightly increases the total time to charge

VCC, but it is generally not noticeable.

Startup Current

Istart

Iinhibit

VCC

Vinhibit

VCC(MIN)

VCC(on)

Figure 27. Startup Current at Various VCC Levels

The start−up circuit is rated at a maximum voltage of

500 V. If the device operates in the DSS mode, power

dissipation should be controlled to avoid exceeding the

maximum power dissipation of the controller. If dissipation

on the controller is excessive, a resistor can be placed in

series with the HV pin. This will reduce power dissipation

on the controller and transfer it to the series resistor.

Standby mode losses and normal mode power dissipation

can be reduced by biasing the controller with an auxiliary

winding. The auxiliary winding needs to maintain VCC

above VCC(MIN) once the startup circuit is disabled.

The power dissipation of the controller when operated in

DSS mode, PDSS, can be calculated using equation 1, where

ICC3 is the operating current of the NCP1218 during

switching and VHV is the voltage at the HV pin. The HV pin

is most often connected to the bulk capacitor.

PDSS + ICC3 @ (VHV * VCC)

(eq. 1)

In comparison, the power dissipation when the startup

circuit is disabled and VCC is being supplied by the

auxiliary winding is a function of the VCC voltage. This is

shown in Equation 2.

PAUX + ICC3 @ VCC

(eq. 2)

It is recommended that an external filter capacitor be

placed as close as possible to the VCC pin to improve the

noise immunity.

Soft−Start Operation

Figures 28 and 29 show how the soft−start feature is

included in the pulse−width modulation (PWM)

comparator. When the NCP1218 starts up, a soft−start

voltage VSSTART begins at 0 V. VSSTART increases

gradually from 0 V to 1.0 V in 4.8 ms and stays at 1.0 V

afterward. VSSTART is compared with the divided by 3

feedback pin voltage (VFB/3). The lesser of VSSTART and

(VFB/3) becomes the modulation voltage, VPWM, in the

PWM duty ratio generation. Initially, (VFB/3) is above

1.0 V because the FB pin is brought to VFB(open), typically

3.6 V, by the internal pullup resistor. As a result, VPWM is

limited by the soft−start function and slowly ramps up the

duty ratio (and therefore the primary current) for the initial

4.8 ms. This provides a greatly reduced stress on the power

devices during startup.

VSSTART

−

VFB/3

)

0

1

VPWM

Figure 28. VPWM is the lesser of VSSTART and (VFB/3)

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