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NCP1207A Просмотр технического описания (PDF) - ON Semiconductor

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NCP1207A Datasheet PDF : 17 Pages
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VCC
12 V
10 V
5.3 V
NCP1207A, NCP1207B
REGULATION
OCCURS HERE
LATCHOFF
PHASE
DRV
INTERNAL
FAULT FLAG
DRIVER
PULSES
TIME
TIME
If the fault is relaxed during the VCC
natural fall down sequence, the IC
automatically resumes.
If the fault still persists when VCC
reached VCCON, then the controller
cuts everything off until recovery.
STARTUP PHASE
FAULT IS
RELAXED
FAULT OCCURS HERE
TIME
Figure 24.
Soft-Start
The NCP1207A/B features an internal 1 ms soft-start to
soften the constraints occurring in the power supply during
startup. It is activated during the power on sequence. As
soon as VCC reaches VCCOFF , the peak current is gradually
increased from nearly zero up to the maximum clamping
level (e.g. 1.0 V). The soft-start is also activated during the
overcurrent burst (OCP) sequence. Every restart attempt is
followed by a soft-start activation. Generally speaking, the
soft-start will be activated when VCC ramps up either from
zero (fresh power-on sequence) or 5.3 V, the latchoff
voltage occurring during OCP.
corresponding IC consumption, including the MOSFET
drive, establishes at 1.8 mA (e.g. with an 11 nC MOSFET),
we can calculate the required capacitor using the following
formula:
Dt
+
DV @
i
C,
with
DV
=
2.0ĂV.
Then
for
a
wanted
Dt of 10 ms, C equals 9.0 mF or 22 mF for a standard value.
When an overload condition occurs, the IC blocks its
internal circuitry and its consumption drops to 330ĂmA
typical. This happens at VCC = 10ĂV and it remains stuck
until VCC reaches 5.3ĂV: we are in latchoff phase. Again,
using the calculated 22ĂmF and 330ĂmA current consumption,
this latchoff phase lasts: 313Ăms.
Calculating the VCC Capacitor
As the above section describes, the fall down sequence
depends upon the VCC level: how long does it take for the
VCC line to go from 12 V to 10 V? The required time depends
on the startup sequence of your system, i.e. when you first
apply the power to the IC. The corresponding transient fault
duration due to the output capacitor charging must be less
than the time needed to discharge from 12ĂV to 10ĂV,
otherwise the supply will not properly start. The test consists
in either simulating or measuring in the lab how much time
the system takes to reach the regulation at full load. Let's
suppose that this time corresponds to 6.0Ăms. Therefore a
VCC fall time of 10Ăms could be well appropriated in order
to not trigger the overload detection circuitry. If the
HV Pin Recommended Protection
When the user unplugs a power supply built with a QR
controller such as the NCP1207A/B, one instance can occur:
A negative ringing can take place on pin8 due to a
resonance between the primary inductance and the bulk
capacitor. As any CMOS device, the NCP1207A/B is
sensitive to negative voltages that could appear on it's pins
and could create an internal latch-up condition.
For this reason, we recommend adding a resistor between
the bulk capacitor and the VCC pin.
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