SPT7870 Просмотр технического описания (PDF) - Signal Processing Technologies
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SPT7870 Datasheet PDF : 8 Pages
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Figure 1 - Timing Diagram
N
N+1
tclk
N+2
tpwh
tpwl
CLK
OUTPUT
N-3
DATA
td
N-2
DATA VALID
N-1
DATA VALID
N
THEORY OF OPERATION
The SPT7870 uses a two stage subranging architecture
incorporating a 3-bit flash MSB conversion stage followed by
an 8-bit interpolating folder conversion stage. Digital error
correction logic combines the results of both stages to produce
a 10-bit data conversion digital output.
The analog signal is input directly to the 3-bit flash converter
which performs a 3-bit conversion and in turn drives an internal
DAC used to set the second stage voltage reference level. The
3-bit result from the flash conversion is input to the digital error
correction logic and used in calculation of the upper most
significant bits of the data output.
The analog input is also input directly to an internal track-and-
hold amplifier. The signal is held and amplified for use in the
second stage conversion. The output of this track-and-hold is
input into a summing junction that takes the difference between
the track-and-hold amplifier and the 3-bit DAC output. The
residual is captured by a second track-and-hold which holds
and amplifies this residual voltage.
The residual held by the track-and-hold amplifier is input to an 8-bit
interpolating folder stage for data conversion. The 8-bit converted
data from the folder stage is input into the digital error correction logic
and used in calculation of the lower significant bits.
The error correction logic incorporates a proprietary scheme
for compensation of any internal offset and gain errors that
might exist to determine the 10-bit conversion result. The
resultant 10 bit data conversion is internally latched and
presented on the data output pins via buffered output drivers.
TYPICAL INTERFACE CIRCUIT
The SPT7870 requires few external components to achieve the
stated operation and performance. Figure 2 shows the typical
interface requirements when using the SPT7870 in normal circuit
operation. The following section provides a description of the pin
functions and outlines critical performance criteria to consider for
achieving the optimal device performance.
POWER SUPPLIES AND GROUNDING
The SPT7870 requires the use of two supply voltages, VEE and
VCC. Both supplies should be treated as analog supply sources.
This means the VEE and VCC ground returns of the device
Table I - Data Output Timing Parameters
Timing Parameter
Min Typ Max
fclock
2 MHz
Clock Pulse Width High (tpwh) 4.0 ns
Clock Pulse Width Low (tpwl) 4.0 ns
100 MHz
250 ns
250 ns
Switching Delay (td)
Clock Latency
3 ns
2 clock cycles
should both be connected to the analog ground plane. All other
-5.2 V requirements of the external digital logic circuit should
be connected to the digital ground plane. Each power supply
pin should be bypassed as closely as possible to the device
with .01 µF and 2.2 µF capacitors as shown in figure 2.
The two grounds available on the SPT7870 are AGND and
DGND. DGND is used only for ECL outputs and is to be
referenced to the output pulldown voltage. These grounds
are not tied together internal to the device. The use of ground
planes is recommended to achieve the best performance of
the SPT7870. The AGND and the DGND ground planes
should be separated from each other and only connected
together at the device through an inductance or ferrite bead.
Doing this will minimize the ground noise pickup.
ANALOG INPUT
The SPT7870 has a single-ended analog input with a bipolar
input range from -1 V to +1 V. The bipolar input allows for
easier interface by external op amps when compared to
unipolar input devices. Because the input common mode is
0 V, the external op amp can operate without a voltage offset
on the output, thereby maximizing op amp head room and
minimizing distortion.
In addition, the 0 V common mode allows for a very simple DC
coupled analog input connection if desired. The current drive
requirements for the analog input are minimal when com-
pared to conventional flash converters due to the SPT7870’s
low input capacitance of only 5 pF and very high input
impedance of 150 kΩ.
CLOCK INPUTS
The clock inputs are designed to be driven differentially with
ECL levels. For optimal noise performance, the clock input
rise time should be a maximum of 1.5 ns. Because of this, the
use of fast logic is recommended. The analog input signal is
latched on the rising edge of the CLK.
The clock may be driven single-ended since the NCLK pin is
internally biased to -1.3 V. NCLK may be left open but a .01
µF bypass capacitor from NCLK to AGND is recommended.
NOTE: System performance may be degraded due to in-
creased clock noise or jitter.
The performance of the SPT7870 is specified and tested with
a 50% clock duty cycle. However, at sample rates greater
SPT
4
SPT7870
9/8/98
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