MT9171 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT9171

Integrated Digital Phone Circuit

Zarlink Semiconductor Inc 

MT9171/72

Data Sheet

AC Electrical Characteristics† - Clock Timing - DN Mode (Figures 16 & 17)

Characteristics

Sym. Min. Typ.* Max. Units

Test Conditions

1 C4 Clock Period

tC4P

244

ns

2 C4 Clock Width High or Low

tC4W

122

ns In Master Mode - Note 1

3 Frame Pulse Setup Time

tF0S

50

ns

4 Frame Pulse Hold Time

tF0H

50

ns

5 Frame Pulse Width

tF0W

244

ns

6 10.24 MHz Clock Jitter (wrt C4)

JC

±15

ns Note 2

† Timing is over recommended temperature & power supply voltages.

* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Notes: 1) When operating as a SLAVE the C4 clock has a 40% duty cycle.

2) When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e.,

FC=2.5xfC4). The relative phase between these two clocks (Φ in Fig. 17) is not critical and may vary from

0 ns to tC4P. However, the relative jitter must be less than JC (see Figure 17).

F0

C4

ST-BUS

BIT CELLS

Channel 31 Channel 0 Channel 0

Bit 0

Bit 7

Bit 6

Figure 15 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams

2.0V

C4

0.8V

tC4P

tC4W

2.0V

F0

0.8V

tF0S

tF0W

tF0H

tC4W

Figure 16 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode

2.0V

C4

0.8V

3.0V

OSC1

2.0V

Φ

JC

Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode

20

Zarlink Semiconductor Inc.

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