MT90810AK Просмотр технического описания (PDF) - Mitel Networks

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MT90810AK

Flexible MVIP Interface Circuit

Mitel Networks 

MT90810

Preliminary Information

framing signal in the group is asserted. The distance

between consecutive frame pulses within a frame

group can be one 2, 4 or 8Mb/s channel time and

can be specified by two bits in the frame mode

register.

Mode 3 is identical to mode 2 except the polarity of

the framing pulses is logically inverted.

Refer to Tables 13 to 16 for details on the frame start

and frame mode registers.

All the framing signals FGA[0:11] and FGB[0:11] are

available in the 100 pin PQFP package.

Delay through the MT90810

Switching delay through the FMIC is dependent on

input and output stream, source and destination

channel, as well as, I/O data rate. A summary of

throughput delay values for the device is provided in

Table 1, “Throughput Delay Values” . The minimum

delay achievable in the MT90810 depends on the

data rate selected for the streams. When switching

from a slower input data rate to a faster output data

rate, the minimum delay is set by the faster output

data rate and the maximum delay is set by the

slower input data rate. When switching from a faster

input data rate to a slower output data rate, the

minimum delay is set by the slower output data rate

and the maximum delay is set by the faster input

data rate.

Input - Output

Rate

Throughput Delay

min

max

2.048 - 2.048Mb/s 2 x 2Mb/s t.s. 1 fr. + 2 x 2Mb/s t.s.

4.096 - 4.096Mb/s 3 x 4Mb/s t.s. 1 fr. + 5 x 4Mb/s t.s.

8.192 - 8.192Mb/s 5 x 8Mb/s t.s. 1 fr. + 11 x 8Mb/s t.s.

2.048 - 4.096Mb/s 3 x 4Mb/s t.s. 1 fr. + 2 x 2Mb/s t.s.

2.048 - 8.192Mb/s 5 x 8Mb/s t.s. 1 fr. + 2 x 2Mb/s t.s.

4.096 - 2.048Mb/s 2 x 2Mb/s t.s. 1 fr. + 5 x 4Mb/s t.s.

8.192 - 2.048Mb/s 2 x 2Mb/s t.s. 1 fr. + 11 x 8Mb/s t.s.

Table 1 - Throughput Delay Values

t.s.=timeslot is used synonymously with channel

fr.=125µs frame

2Mb/s t.s.=3.9µs

4Mb/s t.s.=1.95µs

8Mb/s t.s.=0.975µs

Initialization of the MT90810

The RESET pin should be hold low during

initialization and power-up to ensure that all internal

registers and connection and data memories are

cleared.

2-154

Microprocessor Interface

The FMIC is configured and controlled via a

microprocessor interface. The microprocessor

interface consists of the combined address/data bus

AD[0:7], address bits A[0:1], the chip select bit CS,

the RD and WR signals, the address latch enable

(ALE) signal and the RDY signal. If ALE is tied to

VSS, the interface acts as an Intel nonmultiplexed

interface with the AD[0:7] bus carrying only data and

pins A[0:1] serving as the address lines. If ALE is

tied to VCC the interface acts as a Motorola

nonmultiplexed interface using A[0:1] as address

lines with RD becoming DS and WR becoming R/W.

If ALE is active (switching during accesses), the

interface acts as in Intel multiplexed interface with

the AD[0:7] bus carrying both address and data and

the A[0:1] pins unused. The RDY signal acts as

IOCHRDY in Intel mode and as DTACK in Motorola

mode.

In all modes the FMIC decodes four read/write

registers in the microprocessor’s address space

according to Table 2, “FMIC I/O Addresses”.

Address

A[1:0]

Register

0 [00]

MCS - Master Control/Status Register

1 [01]

2 [10]

LAR - Low Address Register

AMR - Address Mode Register

3 [11]

IDR - Indirect Data Register

Table 2 - FMIC I/O Addresses

The microprocessor interface provides read and

write access to all the registers. When the

microprocessor performs a read or write to the

registers, the microprocessor cycle is a fast cycle (In

Intel mode, the RDY bit is not pulled low, and in

Motorola mode, DTACK is asserted immediately).

When the microprocessor performs a read or write to

data memory or connection memory, the

microprocessor cycle is a slow cycle (In Intel mode,

the RDY is pulled low until the cycle is complete, in

Motorola mode DTACK is not asserted until the cycle

is complete).

Software Control

The FMIC control registers as well as the connection

memory and data memory are accessible through

indirect addressing.

To perform a write operation to an indirect location,

the Low Address Register (LAR) and Address Mode

Register (AMR) registers must first be initialized. The

lower 8 bits of the indirect address are written to the

LAR, and then the upper bit of the indirect address

along with the appropriate bit settings to select the

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