MT9074 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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производитель

MT9074

T1/E1/J1 Single Chip Transceiver

Zarlink Semiconductor Inc 

MT9074

Data Sheet

2. The multiframe counters may be reset with the external hardware pin TxMF. If this signal is not synchronous with

the current transmit frame count it may cause the far end to go temporarily out of sync.

3. Under software control (by setting the TxSYNC bit in page 01 address 12H) the transmit multiframe counters will

be synchronized to the framing pattern present in the overhead bits multiplexed into channel 31 bit 0 of the

incoming 2.048 Mb/s digital stream DSTi. Note that the overhead bits extracted from the receive signal are mul-

tiplexed into outgoing DSTo channel 31 bit 0.

4. In SLC - 96 mode the transmit frame counters synchronize to the framing pattern clocked in on the TXDL input.

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Zarlink Semiconductor Inc.

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