MT9076BPR1 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MT9076BPR1 Datasheet PDF : 172 Pages
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MT9076B
Data Sheet
Time slot 16 of the remaining 15 basic frames of the CAS multiframe (i.e., basic frames 1 to 15) are reserved for the
ABCD signaling bits for the 30 payload channels. The most significant nibbles are reserved for channels 1 to 15 and
the least significant nibbles are reserved for channels 16 to 30. That is, time slot 16 of basic frame 1 has ABCD for
channel 1 and 16, time slot 16 of basic frame 2 has ABCD for channel 2 and 17, through to time slot 16 of basic
frame 15 has ABCD for channel 15 and 30.
4.0 MT9076 Access and Control
4.1 The Control Port Interface
The control and status registers of the MT9076 are accessible through a non-multiplexed parallel microprocessor
port. The parallel port may be configured for Motorola style control signals (by setting pin INT/MOT low) or Intel
style control signals (by setting pin INT/MOT high).
4.2 Control and Status Register Access
The controlling microprocessor gains access to specific registers of the MT9076 through a two step process.
First, writing to the Command/Address Register (CAR) selects one of the 15 pages of control and status
registers (CAR address: AC4 = 0, AC3-AC0 = don't care, CAR data D7 - D0 = page number). Second, each
page has a maximum of 16 registers that are addressed on a read or write to a non-CAR address (non-CAR:
address AC4 = 1, AC3-AC0 = register address, D7-D0 = data). Once a page of memory is selected, it is only
necessary to write to the CAR when a different page is to be accessed. See the AC Electrical Characteristics
section.
Page Address D7 - D0
Register Description
00000001 (01H)
00000010 (02H)
Master
Control
00000011 (03H)
00000100 (04H)
Master
Status
00000101 (05H) Per Channel Transmit signaling
00000110 (06H) Per Channel Transmit signaling
00000111 (07H) Per Time Slot Control
00001000 (08H) Per Time Slot Control
00001001 (09H) Per Channel Receive signaling
00001010 (0AH) Per Channel Receive signaling
00001011 (0BH) HDLC0 Control and Status
00001011 (0CH) HDLC1 Control and Status
00001011 (0DH) HDLC2 Control and Status
00001011 (0EH) Tx National Bit Buffer
00001011 (0FH) Rx National Bit Buffer
Processor Access
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
ST-BUS Access
---
---
CSTi
CSTi
---
---
CSTo
CSTo
--
--
--
--
--
Table 13 - Page Summary
Please note that for microprocessors with read/write cycles less than 200 ns, a wait state or a dummy operation (for
C programming) between two successive read/write operations to the HDLC FIFO is required.
Table 13 associates the MT9076 control and status pages with access and page descriptions.
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