128M16 Просмотр технического описания (PDF) - Micron Technology

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128M16

DDR3 SDRAM

Micron Technology 

2Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol

A[14:13], A12/BC#,

A11, A10/AP, A[9:0]

BA[2:0]

CK, CK#

CKE

CS#

DM

ODT

RAS#, CAS#, WE#

RESET#

Type

Input

Input

Input

Input

Input

Input

Input

Input

Input

Description

Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank

(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also

provide the op-code during a LOAD MODE command. Address inputs are referenced

to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 113).

Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode

register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.

BA[2:0] are referenced to VREFCA.

Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of

CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-

pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE

LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks

idle), or active power-down (row active in any bank). CKE is synchronous for power-

down entry and exit and for self refresh entry. CKE is asynchronous for self refresh

exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during

POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF

REFRESH. CKE is referenced to VREFCA.

Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to VREFCA.

Input data mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with the input data during a write access.

Although the DM ball is input-only, the DM loading is designed to match that of the

DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on

the x8.

On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,

and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is

ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA.

Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to VREFCA.

Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and

DC LOW ≤ 0.2 × VDDQ. RESET# assertion and de-assertion are asynchronous.

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

‹ 2006 Micron Technology, Inc. All rights reserved.

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