MT16VDDF6464H(2008) Просмотр технического описания (PDF) - Micron Technology

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производитель

MT16VDDF6464H
(Rev.:2008)

DDR SDRAM SODIMM

Micron Technology 

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Serial Presence-Detect

Serial Presence-Detect

Table 12: Serial Presence-Detect EEPROM DC Operating Conditions

Parameter/Condition

Supply voltage

Input high voltage: Logic 1; All inputs

Input low voltage: Logic 0; All inputs

Output low voltage: IOUT = 3mA

Input leakage current: VIN = GND to VDD

Output leakage current: VOUT = GND to VDD

Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VDD or VSS

Power supply current: SCL clock frequency = 100 kHz

Symbol

VDDSPD

VIH

VIL

VOL

ILI

ILO

ISB

ICC

Min

Max

2.3

3.6

VDDSPD × 0.7 VDDSPD + 0.5

–1.0

VDDSPD × 0.3

–

0.4

–

10

–

10

–

30

–

2.0

Units

V

V

V

V

µA

µA

µA

mA

Table 13: Serial Presence-Detect EEPROM AC Operating Conditions

Parameter/Condition

SCL LOW to SDA data-out valid

Time the bus must be free before a new transition can start

Data-out hold time

Clock/data fall time

Clock/data rise time

Data-in hold time

Start condition hold time

Clock HIGH period

Noise suppression time constant at SCL, SDA inputs

Clock LOW period

SCL clock frequency

Data-in setup time

Start condition setup time

Stop condition setup time

WRITE cycle time

Symbol

tAA

tBUF

tDH

tF

tR

tHD:DAT

tHD:STA

tHIGH

tI

tLOW

fSCL

tSU:DAT

tSU:STA

tSU:STO

tWRC

Min

0.2

1.3

200

–

–

0

0.6

0.6

–

1.3

–

100

0.6

0.6

–

Max

0.9

–

–

300

300

–

–

–

50

–

400

–

–

–

10

Units

µs

µs

ns

ns

ns

µs

µs

µs

ns

µs

kHz

ns

µs

µs

ms

Notes

1

2

2

3

4

Notes:

1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and

the falling or rising edge of SDA.

2. This parameter is sampled.

3. For a restart condition or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write

sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE

cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-

tor, and the EEPROM does not respond to its slave address.

Serial Presence-Detect Data

For the latest serial presence-detect data, refer to Micron’s SPD page:

www.micron.com/SPD.

PDF: 09005aef80a77a90/Source: 09005aef80a646bc

DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

13

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc. All rights reserved

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