MSM6262-XX Просмотр технического описания (PDF) - Oki Electric Industry

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MSM6262-XX

DOT MATRIX LCD CONTROLLER WITH 48-DOT COMMON DRIVER

Oki Electric Industry 

¡ Semiconductor

MSM6262-xx

(10) DD RAM address set

A1 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction H

code

L

AI7 AI6 AI5 AI4 AI3 AI2 AI1 AI0

This instruction code sets the DD RAM address, which consists of 8 bits (AI7 to AI0). The

data which is received after this instruction is set is limited to the DD RAM data (character

code data).

Do not input any address code other than those below.

2-line mode : 1st line 00 - 4F

2nd line 80 - CF

4-line mode : 1st line 00 - 27

2nd line 40 - 67

3rd line 80 - A7

4th line C0 - E7

(11) Underline data read

A1 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction L

code

L ULD D06 D05 D04 D03 D02 D01 D00

This instruction reads underline data, and CG RAM or DD RAM data.

Determination of CG RAM or DD RAM is made by the previously set CG RAM or DD

RAM address set.

The first data read by this instruction is an invalied data. Normal data is read out from

the second instruction onward if the read instruction is executed continuously. This

instruction address will be incremented or decremented by 1 according to the entry

mode. Display shift is, however, not performed. Underline data is output to DB7 as either

"H" (when display is on) or "L" (when display is off).

The MSB of RAM data is not read. RAM data consists of 7 bits (DB0 to DB6).

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