MSM6262 Просмотр технического описания (PDF) - Oki Electric Industry

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производитель

MSM6262

DOT MATRIX LCD CONTROLLER WITH 48-DOT COMMON DRIVER

Oki Electric Industry 

¡ Semiconductor

MSM6262-xx

as the input data.

Since the ADC is automatically incremented or decremented by 1 after the writing of data

to the CG RAM, it is not necessary to set the CG RAM address again.

To enable cursor display, set all input data on the line where the CG RAM address is "0B"

or "1B" (hex.) to "L".

The addresses "0" to "B" (hexadecimal) in the bits 0 to 4 of the CG RAM data are output on

the LCD as the display data. However, the addresses "C" to "F" (hexadecimal) in the bits

0 to 4, and 5 to 7 of the CG RAM data are not output on the LCD. But these CG RAM data

can be used as the data RAM so that they can be written into or read out through DB0 to

DB7.

• A method to display the CG RAM character pattern on the LCD

First, an instruction to enable the CG RAM has to be input from the CPU. CG RAM is

selected only when all of the upper 4 bits of the character code is "L".

So, the character pattern of CG RAM is displayed on the LCD position corresponding to

the DD RAM address, when the character code shown in Table 2-2 is written into the DD

RAM.

Since bits 0, 2 and 3 of the character code are regarded as invalid, the character of "m" is

displayed when the character codes "00", "01", "04", "05", "08", "09", "0C" and "0D" are

selected.

(3) A method to read out the CG RAM data

First, set the CG RAM address by inputting a CG RAM address set instruction from the

CPU.

Then, execute the CG RAM/DD RAM data read instruction. The set data of CG RAM

address is output from the DB0 to DB7. The 8-bit data, read out from the MSM6262-xx,

corresponds to the data which is written into the CG RAM. Since the CG RAM address is

automatically incremented or decremented by 1, the CG RAM read out instruction c a n

be successfully input. It is necessary, however, to set the DD RAM at data transferring

condition by executing the DD RAM address set instruction after all of CG RAM data are

read out.

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