MPC7445 Просмотр технического описания (PDF) - Freescale Semiconductor
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MPC7445 Datasheet PDF : 64 Pages
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Electrical and Thermal Characteristics
5.2.2 Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7455 as defined in Figure 4 and Figure 5.
Timing specifications for the L3 bus are provided in Section 5.2.3, “L3 Clock AC Specifications.”
Table 9. Processor Bus AC Timing Specifications 1
At recommended operating conditions. See Table 4.
Parameter
Input setup times:
A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], TT[0:3], D[0:63],
DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], QACK, TA,
TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1]
BMODE[0:1], BVSEL, L3VSEL
Input hold times:
A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], TT[0:3], D[0:63],
DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], QACK, TA,
TBEN, TEA, TS,EXT_QUAL, PMON_IN, SHD[0:1]
BMODE[0:1], BVSEL, L3VSEL
Output valid times:
A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], TT[0:3], WT, CI
TS
D[0:63], DP[0:7]
ARTRY/SHD0/SHD1
BR, CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ]
Output hold times:
A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], TT[0:3], WT, CI
TS
D[0:63], DP[0:7]
ARTRY/SHD0/SHD1
BR, CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ
SYSCLK to output enable
SYSCLK to output high impedance (all except TS, ARTRY,
SHD0, SHD1)
SYSCLK to TS high impedance after precharge
Maximum delay to ARTRY/SHD0/SHD1 precharge
Symbol 2
All Speed Grades
Min
Max
tAVKH
2.0
—
tIVKH
2.0
—
Unit
ns
Notes
tMVKH
2.0
—
8
ns
tAXKH
0
—
tIXKH
0
—
tMXKH
0
tKHAV
—
tKHTSV
—
tKHDV
—
tKHARV
—
tKHOV
—
tKHAX
0.5
tKHTSX
0.5
tKHDX
0.5
tKHARX
0.5
tKHOX
0.5
tKHOE
0.5
tKHOZ
—
tKHTSPZ
—
tKHARP
—
—
8
ns
2.5
2.5
2.5
2.5
2.5
ns
—
—
—
—
—
—
ns
3.5
ns
1
tSYSCLK
3, 4, 5
1
tSYSCLK
3, 5,
6, 7
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
17
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