Electrical and Thermal Characteristics
60x Bus Clock
Group I, II, III,
and IV INPUTS
VM
10a
11a
SYSCLK
VM
10b
11b
Group V and
VI INPUTS
VM = Midpoint Voltage (1.4 V)
Figure 3. Input Timing Diagram
Figure 4 provides the mode select input timing diagram for the 106.
HRST
VM
10c
11c
MODE PINS
VM = Midpoint Voltage (1.4 V)
Figure 4. Mode Select Input Timing Diagram
1.4.2.3 Output AC Specifications
Table 8 provides the output AC timing specifications for 106 (shown in Table 5). Assume Vdd = AVdd =
3.3 ± 5% V DC, GND = 0 V DC, CL = 50 pF, and 0 ≤ Tj ≤ 105 °C. Processor and memory interface signals
are specified from the rising edge of the 60x bus clock (which is internally synchronized to SYSCLK). All
units are nanoseconds.
10
MPC106 PCI Bridge/Memory Controller Hardware Specifications