ML674000 Просмотр технического описания (PDF) - Oki Electric Industry
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ML674000 Datasheet PDF : 24 Pages
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OKI Semiconductor
FEDL674000-02
ML674000
Pin Name I/O
Description
Primary/ Logic
Secondary
DMA control signals
DREQ0
Ch 0 DMA request signal, used when DMA controller configured for DREQ
I type
Secondary Positive
DREQCLR0
Ch 0 DREQ signal clear request. The DMA device responds to this output by
O negating DREQ.
Secondary Positive
TCOUT0
O Indicates to Ch 0 DMA device that last transfer has started
Secondary Positive
DREQ1
Ch 1 DMA request signal, used when DMA controller configured for DREQ
I type
Secondary Positive
DREQCLR1
Ch 1 DREQ signal clear request. The DMA device responds to this output by
O
Secondary Positive
negating DREQ.
TCOUT1
O Indicates to Ch 1 DMA device that last transfer has started
Secondary Positive
SIO
STXD
O SIO transmit signal
Secondary Positive
SRXD
I SIO receive signal
Secondary Positive
UART
SIN
I Serial data input
Secondary Positive
SOUT
O Serial data output
Secondary Positive
CTS
Clear To Send.
I Indicates that modem or data set is ready to transfer data.
Bit 4 in modem status register reflects this input.
Secondary Negative
DSR
Data Set Ready.
Indicates that modem or data set is ready to establish a communications link
I with UART.
Secondary Negative
Bit 5 in modem status register reflects this input.
DCD
Data Carrier Detect.
I Indicates that modem or data set has detected data carrier signal.
Bit 7 in modem status register reflects this input.
Secondary Negative
DTR
Data Terminal Ready.
Indicates that UART is ready to establish a communications link with
O modem or data set.
Bit 0 in modem control register controls this output.
Secondary Negative
Request To Send.
RTS
O Indicates that UART is ready to transfer data to modem or data set.
Secondary Negative
Bit 1 in modem control register controls this output.
Ring Indicator.
RI
I Indicates that modem or data set has received telephone ring indicator.
Secondary Negative
Bit 6 in modem status register reflects this input.
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