ML2652 Просмотр технического описания (PDF) - Micro Linear Corporation
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ML2652 Datasheet PDF : 23 Pages
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FUNCTIONAL DESCRIPTION (Continued)
Then the NRZ data is encoded by the manchester encoder
as shown in transmit timing diagram in Figure 1.
The manchester encoded data then goes to either the AUI
or twisted pair interface. The selection of the appropriate
interface is automatic. If the AUI is selected, the
manchester encoded data is transmitted out differentially
on the DO+ and DO– pins, and the twisted pair line driver
is disabled. If the twisted pair interface is selected, the
manchester encoded data is transmitted out differentially
on Tx+ and Tx– pins, and the transmit AUI is disabled.
Refer to the AUI section for details on how the AUI and
automatic interface selection is accomplished.
Assuming that the twisted pair interface is selected, the
Manchester encoded data then goes to the transmit
waveform generator. The transmit waveform generator
takes the digital Manchester encoded data and generates a
waveform. When this waveform is passed through the
cable model in the 10BASE-T standard (figure 14–7 IEEE
Std 802.3i–1990) it meets the voltage template (figure 14–
9 IEEE Std 802.3i–1990).
The transmit waveform generator is composed of a 16 x 4
bit ROM, 4 bit DAC, 3rd order LPF, and clock generator.
The DAC is used to synthesize a stair-step representation of
a signal that will meet the required output template. The
ROM stores the digital representation of the output signal
and provides a digital input to the DAC. The ROM is
addressed by a 16 phase clock generator that is locked to
the transmit clock TxC. The high frequency content present
in the output of the DAC is removed by a 3rd order
continuous LPF which smooths the output.
The transmit line driver takes the output of the waveform
generator and converts this voltage to a differential output
current on Tx+ and Tx– pins. When one transmit output
(either Tx+ or Tx–) is sinking current, the other output is
high impedance, and vice versa. In this way, a differential
output voltage is developed by sinking this output current
through two external 200 ohm terminating resistor and a
2:1 transformer as shown in Figure 12.
Setting the external terminating resistors to 200 ohms as
shown in Figure 12 will implement a 100 ohm terminating
impedance when looking back through the transformer. If
other terminating impedances are required (such as 150
ohm), the terminating resistor values can be adjusted
accordingly as long as the output current stays within the
minimum and maximum limits (30–70mA).
The absolute value of the output current, and subsequently
the output voltage level, is set by an external resistor
between RTX and GND. If RTX = 10k ohms and Tx± is
terminated as shown in Figure 12, the output level is
±2.5V which meets 802.3i–1990 differential output
voltage requirements. If a different output current/voltage
level is desired, the level can be changed by changing the
value of RTX according to the following formula:
ML2652/ML2653
RTX = K*Vb/Iout
= 125*4v/50mA
RTX = 10kW
When data is being transmitted (and there is no collision
or link pulse fail condition), the transmit data is looped
back to the receive path, and the Manchester decoder will
lock onto the transmit data stream.
After data transmission is completed, the transmitter sends
a start of idle (SOI) pulse to signal the end of a packet.
During the idle period, Tx+ and Tx– are held low.
Occasionally, link pulses are transmitted during the idle
period.
The XMT pin is an output that indicates transmit activity.
The pin consists of an open drain output with an internal
pull-up resistor and can drive an LED from VCC or another
digital input. In order to make an LED visible, XMT has an
internal blinker circuit that generates a 100ms blink (50ms
high, 50ms low) that is triggered when a trans-mission
starts. At the completion of the 100ms blink period, if a
transmission is in progress, another 100ms blink is
generated.
RECEPTION
The twisted pair receive data is typically transformer
coupled and terminated with an external resistor as shown
in Figure 12.
The output of the transformer is then applied to the device
input pins Rx+ and Rx–. The input is differential, and the
common mode input voltage is biased to VCC/2 by two
internal 10K bias resistors from Rx+, Rx– to VCC/2.
The Rx+ and Rx– inputs then go to the receive filter. The
receive filter is a continuous 3rd order LPF and has the
following characteristics:
1. 3 dB cut-off frequency
15 MHz
2. Insertion Loss (5–10 MHz) - 1.0 dB
3. 30 MHz attenuation
17.5 dB min.
The output of the filter goes to the receive comparators.
There are two receive comparators inside the chip,
threshold and zero crossing. The threshold comparator
determines if the receive data is valid by checking the
input signal level against a predetermined positive and
negative squelch level. Once the threshold comparator
determines that valid data is being received, the zero
crossing comparator senses zero crossings to determine
data transitions. Both comparators are fast enough to
respond to 12ns pulse widths with minimum squelch
overdrive.
17
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