MK20DX32CLQ15 Просмотр технического описания (PDF) - Freescale Semiconductor

Номер в каталоге

Компоненты Описание

производитель

MK20DX32CLQ15

K20 Sub-Family

Freescale Semiconductor 

General

5.3.2 General switching specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

CAN, CMT, and I2C signals.

Symbol

Table 10. General switching specifications

Description

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter enabled) — Asynchronous path

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter disabled) — Asynchronous path

External reset pulse width (digital glitch filter disabled)

Mode select (EZP_CS) hold time after reset

deassertion

Port rise and fall time (high drive strength)

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

Min.

1.5

100

16

100

2

—

—

—

—

Max.

—

—

—

—

—

12

6

36

24

Unit

Bus clock

cycles

ns

ns

ns

Bus clock

cycles

ns

ns

ns

ns

Notes

1

2

2

2

3

Port rise and fall time (low drive strength)

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

4

—

12

ns

—

6

ns

—

36

ns

—

24

ns

1. The greater synchronous and asynchronous timing must be met.

2. This is the shortest pulse that is guaranteed to be recognized.

3. 75pF load

4. 15pF load

5.4 Thermal specifications

K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.

20

Freescale Semiconductor, Inc.

Share Link: