MFRC523 Просмотр технического описания (PDF) - NXP Semiconductors.

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MFRC523

Contactless Reader IC

NXP Semiconductors. 

NXP Semiconductors

MFRC523

Contactless reader IC

8.4.5 CRC coprocessor

The following CRC coprocessor parameters can be configured:

• The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on

the ModeReg register’s CRCPreset[1:0] bits setting

• The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1

• The CRCResultReg register indicates the result of the CRC calculation. This register

is split into two 8-bit registers representing the higher and lower bytes.

• The ModeReg register’s MSBFirst bit indicates that data will be loaded with the MSB

first.

Table 17. CRC coprocessor parameters

Parameter

Value

CRC register length

16-bit CRC

CRC algorithm

algorithm according to ISO/IEC 14443 A and ITU-T

CRC preset value

0000h, 6363h, A671h or FFFFh depending on the setting of the

ModeReg register’s CRCPreset[1:0] bits

8.5 FIFO buffer

An 8 × 64 bit FIFO buffer is used in the MFRC523. It buffers the input and output data

stream between the host and the MFRC523’s internal state machine. This makes it

possible to manage data streams up to 64 bytes long without the need to take timing

constraints into account.

8.5.1 Accessing the FIFO buffer

The FIFO buffer input and output data bus is connected to the FIFODataReg register.

Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO

buffer write pointer. Reading from this register shows the FIFO buffer contents stored in

the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance

between the write and read pointer can be obtained by reading the FIFOLevelReg

register.

When the microcontroller starts a command, the MFRC523 can, while the command is in

progress, access the FIFO buffer according to that command. Only one FIFO buffer has

been implemented which can be used for input and output. The microcontroller must

ensure that there are not any unintentional FIFO buffer accesses.

8.5.2 Controlling the FIFO buffer

The FIFO buffer pointers can be reset by setting FIFOLevelReg register’s FlushBuffer bit

to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg

register’s BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longer

accessible allowing the FIFO buffer to be filled with another 64 bytes.

8.5.3 FIFO buffer status information

The host can get the following FIFO buffer status information:

• Number of bytes stored in the FIFO buffer: FIFOLevelReg register’s FIFOLevel[6:0]

• FIFO buffer almost full warning: Status1Reg register’s HiAlert bit

MFRC523_33

Product data sheet

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All information provided in this document is subject to legal disclaimers.

Rev. 3.3 — 5 March 2010

115233

© NXP B.V. 2010. All rights reserved.

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