MT90820 Просмотр технического описания (PDF) - Mitel Networks
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MT90820 Datasheet PDF : 10 Pages
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MT90820 CMOS
Advance Information
A7 A6 A5 A4 A3 A2 A1 A0
Location
0
0
0
0
0
0
0
0 Control Register, CAR.
0
0
0
0
0
0
0
1 Interface Mode Selection register, IMS
0
0
0
0
0
0
1
0 Frame Alignment register, FAR
0
0
0
0
0
0
1
1 Frame Input Offset register 0, FOS0
0
0
0
0
0
1
0
0 Frame Input Offset register 1, FOS1
0
0
0
0
0
1
0
1 Frame Input Offset register 2, FOS2
0
0
0
0
0
1
1
0 Frame Input Offset register 3, FOS3
1
0
0
0
0
0
0
0 Ch 0*
1
0
0
0
0
0
0
1 Ch 1*
1
0
0
.
.
.
.
.
.
1
0
0
1
1
1
1
0 Ch 30*
1
0
0
1
1
1
1
1 Ch 31*
1
0
1
0
0
0
0
0 Ch 32**
1
0
1
0
0
0
0
1 Ch 33**
1
0
1
.
.
.
.
.
.
1
0
1
1
1
1
1
0 Ch 62**
1
0
1
1
1
1
1
1 Ch 63**
1
1
0
0
0
0
0
0 Ch 64***
1
1
0
0
0
0
0
1 Ch 65***
1
1
.
.
.
.
.
.
.
1
1
1
1
1
1
1
0 Ch 126***
1
1
1
1
1
1
1
1 Ch 127***
Note 1: The bit A7 must be retained HIGH for accesses to Data and Connection Memory positions.
The bit A7 must be retained LOW for accesses to Registers.
Note*: Channel 0 to 31 are used in 2Meg mode.
Note**: Channel 0 to 63 are used in 4Meg mode.
Note***: Channel 0 to 127 are used in 8Meg mode.
Table 2 - Internal Register and Address Memory Mapping
2-186
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