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MCF5271

MCF5271 Integrated Microprocessor Hardware Specification

Freescale Semiconductor 

— Partial drive strength (Default)

— Full drive strength

• Clock mode:

— Normal PLL with external crystal

— Normal PLL with external clock

— 1:1 PLL Mode

— External oscillator mode (no PLL)

• Chip Select Configuration:

— PADDR[7:5] configured as chip select(s) and/or address line(s)

– PADDR[7:5] configured as A23-A21 (default)

– PADDR configured as CS6, PADDR[6:5] as A22-A21

– PADDR[7:6] configured as CS[6:5], PADDR5 as A21

– PADDR[7:5] configured as CS[6:4]

Modes of Operation

5.1.1 Chip Configuration Pins

Table 3. Configuration Pin Descriptions

Pin

RCON

D16

D20, D19

D21

CLKMOD1,

CLKMOD0

Chip Configuration

Function

Pin State/Meaning

Comments

Chip configuration

enable

1 Disabled

0 Enabled

Active low: if asserted, then all

configuration pins must be driven

appropriately for desired operation

Select chip

operating mode

1 Master

0 Reserved

Select external boot 00,11 External (32-bit)

device data port size 10 External (8-bit)

01 External (16-bit)

Value read defaults to 32-bit

Select output pad

drive strength

1 Full

0 Partial

Select clock mode

00 External clock mode (no VDDPLL must be supplied if a PLL

PLL)

mode is selected

01 1:1 PLL mode

10 Normal PLL with

external clock reference

11 Normal PLL with crystal

clock reference

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

Freescale Semiconductor

17

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