Architecture Block Diagram
5
JTAG / EOnCE
CHIP
TAP
Controller
pdb_m[15:0]
pab[20:0]
cdbw[31:0]
56800E
Boot
Flash
Program
Flash
Program
RAM
24
Address
EMI
16
Data
10
Control
TAP
Linking
Module
xab1[23:0]
xab2[23:0]
Data RAM
External JTAG
Port
cdbr_m[31:0]
xdb2_m[15:0]
Data Flash
IPBus
Bridge
To Flash
Control Logic
Note:
Note:
NOT available on the 56F8167 device.
IPBus
Figure 1-1 System Bus Interfaces
Flash
Memory
Module
Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is
accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed
between the core and the Flash memories.
The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
11
Preliminary