MC100H640 Просмотр технического описания (PDF) - ON Semiconductor
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MC100H640 Datasheet PDF : 9 Pages
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MC10H640, MC100H640
10/100H640
DUTY CYCLE CONTROL
To maintain a duty cycle of ± 5% at 50MHz, limit the load capacitance and/or power supply variation as shown in Figures 3
and 4. For a ± 2.5% duty cycle limit, see Figures 5 and 6. Figures 7 and 8 show duty cycle variation with temperature. Figure 9
shows typical TPD versus load. Figure 10 shows reset recovery time. Figure 11 shows output states after power up.
Best duty cycle control is obtained with a single mP load and minimum line length.
11
11
5.25 VCC
5 VCC
4.75 VCC
10
10
4.75 VCC
5 VCC
9
9
5.25 VCC
0
25
50
75
85
0
25
50
75
85
LOAD (pF)
LOAD (pF)
Figure 3. Positive Pulse Width at
25°C Ambient and 50 MHz Out
Figure 4. Negative Pulse Width at
25°C Ambient and 50 MHz Out
11
11
5.125 VCC
5 VCC
4.875 VCC
10
10
4.875 VCC
5 VCC
5.125 VCC
9
9
0
25
50
75
85
LOAD (pF)
Figure 5. Positive Pulse Width at
25°C Ambient at 50 MHz Out
0
25
50
75
85
LOAD (pF)
Figure 6. Negative Pulse Width at
25°C Ambient at 50 MHz Out
11
11
50 pF
10 pF
25 pF
10
10
25 pF
10 pF
9
9
0°
25°
50°
75° 85°
TEMPERATURE (°C)
Figure 7. Temperature versus Positive Pulse Width
for 100H640 at 50 MHz and VCC = +5.0 V
0°
25°
50°
75° 85°
TEMPERATURE (°C)
Figure 8. Temperature versus Negative Pulse Width
for MC100H640 @ 50 MHz and VCC = +5.0 V
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