MBM29DL800BA-70 Просмотр технического описания (PDF) - Spansion Inc.

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производитель

MBM29DL800BA-70

8M (1M X 8/512K X 16) BIT

Spansion Inc. 

MBM29DL800TA-70/90/MBM29DL800BA-70/90

to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin

becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always

an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer

to “(10) Timing Diagram for Word Mode Configuration” and “(11) Timing Diagram for Byte Mode Configuration”

and “(12) BYTE Timing Diagram for Write Operations” in sTIMING DIAGRAM for the timing diagram.

Data Protection

The MBM29DL800TA/BA are designed to offer protection against accidental erasure or programming caused

by spurious system level signals that may exist during power transitions. During power up the devices

automatically reset the internal state machine in the Read mode. Also, with its control register architecture,

alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command

sequences.

The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up

and power-down transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less

than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits

are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until

the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct

to prevent unintentional writes when VCC is above 2.3 V.

If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

Sector Protection

Device user is able to protect each sector individually to store and protect data. Protection circuit voids both

program and erase commands that are addressed to protected sectors.

Any commands to program or erase addressed to protected sector are ignored (see “Sector Protection” in

s FUNCTIONAL DESCRIPTION)

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