MBM29DL800BA-70 Просмотр технического описания (PDF) - Spansion Inc.

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MBM29DL800BA-70

8M (1M X 8/512K X 16) BIT

Spansion Inc. 

MBM29DL800TA-70/90/MBM29DL800BA-70/90

Reading Toggle Bits DQ6/DQ2

Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row

to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle

bit after the first read. After the second read, the system would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, this indicates that the device has completed the program or erase operation.

The system can read array data on DQ7 to DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system

also should note whether the value of DQ5 is high (see “the section on DQ5”) . If it is the system should then

determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5

went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase

operation. If it is still toggling, the device did not complete the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous paragraph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine

the status of the operation (See “(4) Toggle bit algorithm” in sFLOW CHART) .

Toggle Bit Status Table

Mode

DQ7

DQ6

DQ2

Program

DQ7

Toggle

1

Erase

0

Toggle

Toggle*1

Erase-Suspend Read

(Erase-Suspended Sector)

1

1

Toggle

Erase-Suspend Program

DQ7

Toggle

1*2

*1 : Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle.

*2 : Reading from non-erase suspend sector address indicates logic “1” at the DQ2 bit.

RY/BY

Ready/Busy

The MBM29DL800TA/BA provide a RY/BY open-drain output pin as a way to indicate to the host system that

the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are

busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/

write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase

commands. If the MBM29DL800TA/BA are placed in an Erase Suspend mode, the RY/BY output will be high.

During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate

a busy condition during the RESET pulse. Refer to “(8) RY/BY Timing Diagram during Program/Erase

Operations” and “(9) RESET/RY/BY Timing Diagram” in sTIMING DIAGRAM for a detailed timing diagram. The

RY/BY pin is pulled high in standby mode.

Since this is an open-drain output, the pull-up resistor needs to be connected to VCC; multiples of devices may

be connected to the host system via more than one RY/BY pin in parallel.

Byte/Word Configuration

The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL800TA/BA devices. When

this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0

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