MBM29DL800BA-70 Просмотр технического описания (PDF) - Spansion Inc.

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MBM29DL800BA-70

8M (1M X 8/512K X 16) BIT

Spansion Inc. 

MBM29DL800TA-70/90/MBM29DL800BA-70/90

DQ7

Data Polling

The MBM29DL800TA/BA devices feature Data Polling as a method to indicate to the host that the Embedded

Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the

devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program

Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded

Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the

Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart

for Data Polling (DQ7) is shown in “(3) Data Polling Algorithm” in sFLOW CHART.

For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse

sequence.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased

and not a protected sector. Otherwise, the status may not be valid.

If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then

that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for

erasing are protected, Data Polling on DQ7 is active for approximately 100 µs, then the bank returns to read mode.

Once the Embedded Algorithm operation is close to being completed, the MBM29DL800TA/BA data pins (DQ7)

may change asynchronously while the output enable (OE) is asserted low. This means that the devices are

driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time.

Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device

has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6

may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts.

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm

or sector erase time-out. (See “Hardware Sequence Flags Table”.)

See “(6) AC Waveforms for Data Polling during Embedded Algorithm Operations” in sTIMING DIAGRAM for the

Data Polling timing specifications and diagrams.

DQ6

Toggle Bit I

The MBM29DL800TA/BA also feature the “Toggle Bit I” as a method to indicate to the host system that the

Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from

the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During

programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.

For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop

toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the

ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs

and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will

cause the DQ6 to toggle.

The system can use DQ6 to determine whether a sector is actively erasing or is erase-suspended. When a bank

is actively erasing (that is, the Embedded Erase Algorithm is in progress), DQ6 toggles. When a bank enters the

Erase Suspend mode, DQ6 stops toggling. Successive read cycles during the erase-suspend-program cause

DQ6 to toggle.

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