MBM29F080A Просмотр технического описания (PDF) - Spansion Inc.

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MBM29F080A

FLASH MEMORY CMOS 8M (1M ×8) BIT

Spansion Inc. 

MBM29F080A-55/-70/-90

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase

Algorithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out. (See “Hardware Sequence

Flags Table” in “sFLEXIBLE SECTOR-ERASE ARCHITECTURE”.)

See “AC Waveforms for Data Polling during Embedded Algorithm Operations” in “sTIMING DIAGRAM” for the

Data Polling timing specifications and diagrams.

DQ6

Toggle Bit I

The MBM29F080A also features the “Toggle Bit I” as a method to indicate to the host system that the embedded

algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from

the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or

Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive

attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four

write pulse sequence. For chip erase, and sector erase the Toggle Bit I is valid after the rising edge of the sixth

WE pulse in the six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of

the sector erase WE pulse. The Toggle Bit I is active during the sector erase time out.

In programming, if the sector being written to is protected, the Toggle Bit I will toggle for about 2 µs and then

stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for

the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about

100 µs and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will

cause DQ6 to toggle.

See “AC Waveforms for Toggle Bit I during Embedded Algorithm Operations” in “sTIMING DIAGRAM” for the

Toggle Bit I timing specifications and diagrams.

DQ5

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling DQ7, DQ6 is the only operating function of the device under

this condition. The CE circuit will partially power down the device under these conditions (to approximately 2

mA). The OE and WE pins will control the output disable functions as described in “MBM29F080A User Bus

Operations Table” in “sFLEXIBLE SECTOR-ERASE ARCHITECTURE”.

The DQ5 failure condition may also appear if a user tries to program a 1 to a location that is previously programmed

to 0. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the

system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing

limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was

incorrectly used. If this occurs, reset the device.

DQ3

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will

remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase

command sequence.

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