MB86961APD-G Просмотр технического описания (PDF) - Fujitsu

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MB86961APD-G

UNIVERSAL INTERFACE FOR 10BASE -T

Fujitsu 

MB86961A

MODE 3 (MD1=1, MD0=0) TIMING DIAGRAMS — FIGURES 24 - 29

TPIP/TPIN

CD

10101010111010001010

tCD

RCLK

RXD

tDATA

tRDH

tRDS

1 0 1 0 1 0 1 0 1 1 1 01

Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.

Figure 24. Mode 3 RCLK/SOP Timing

TPIP/TPIN

CD

RCLK

101010100

tCDOFF

tRD

tIFG

27 Bits

RXD

101010100

Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.

Figure 25. Mode 3 RCLK/EOP Timing

23

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