MB86961APF-G Просмотр технического описания (PDF) - Fujitsu

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MB86961APF-G

UNIVERSAL INTERFACE FOR 10BASE -T

Fujitsu 

MB86961A

MODE 2 (MD1=0, MD0=1) TIMING DIAGRAMS — FIGURES 18 - 23

TPIP/TPIN

CD

10101010111010001010

tCD

RCLK

RXD

tDATA

tRDH

tRDS

1 0 1 0 1 0 1 0 1 1 1 01

Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.

Figure 18. Mode 2 RCLK/SOP Timing

TPIP/TPIN

101010100

CD

tRD

RCLK

tCDOFF

tIFG

RXD

101010100

Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.

Figure 19. Mode 2 RCLK/EOP Timing

21

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