MB86960APF-G Просмотр технического описания (PDF) - Fujitsu
Номер в каталоге
Компоненты Описание
производитель
MB86960APF-G Datasheet PDF : 65 Pages
| |||
MB86960
Configuration Registers 0 and 1
Basic system configuration bits are found in these two
registers. Among the configuration controls found here
are physical packet buffer memory size, partitioning
between transmit and receive buffers, widths of memory
and system buses, byte lane control, chip configuration
and power down control. Most of these configuration
parameters will be programmed only during initialization
after power start and hardware reset. See Tables 12 and
13.
Table 12. DLCR6 — Configuration Register 0
BIT SYMBOL TYPE
DESCRIPTION
7
DLC EN
R ENABLE DATA LINK CONTROLLER: When low, enables the receiver and transmitter
W sections of the NICE chip. This bit must be set high during initialization and later set low to
1 enable loopback testing and operation of the network. Program NODE ID only when this bit is
high.
6
1
N RESERVED: Write 1.
0
5
SB/SW
R SYSTEM BYTE/WORD BUS WIDTH: When high, system bus will operate in 8-bit data
W mode; when low, 16-bit data mode is selected. See also BB/BW below.
1
4
BB/BW
R BUFFER BYTE/WORK WIDTH: When high, buffer memory will operate in 8-bit data
W mode; when low, 16-bit data mode is selected. See table for allowable combinations with
1 SB/SW:
SB/SW
0
0
1
1
BB/BW
0
1
0
1
SYSTEM
BUFFER
word
word
word
byte
Do not use
byte
byte
3, 2 TBS 1, 0
R
TRANSMIT BUFFER SIZE: Selects size of Transmit Buffer(s). See table:
W
01
TBS
No. TX
Size each Total Size
1,0
BUFS
TX BUF
TX BUF
00
1
2KB
2KB
01
2
2KB
4KB
10
2
4KB
8KB
11
2
8KB
16KB
1, 0
BS1, 0
R BUFFER SIZE: Selects physical size of total SRAM buffer memory for both transmit and
W receive functions. See table:
10
BS1
BS0
SRAM Size
0
0
8KB
0
1
16KB
1
0
32KB
1
1
64KB
Share Link: 