MB15F03SL Просмотр технического описания (PDF) - Fujitsu

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Компоненты Описание

производитель

MB15F03SL

Dual Serial Input PLL Frequency Synthesizer

Fujitsu 

MB15F03SL

Programmable Counter

LSB

Data Flow

MSB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

C

N

1

C

N

2

L

D

S

S

W

IF/RF

F

C

IF/RF

A

1

A

2

A

3

A

4

A

5

A

6

A

7

N

1

N

2

N

3

N

4

N

5

N

6

N

7

N

8

NNN

9 10 11

CNT1, 2 : Control bit

N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)

A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)

SWIF/RF : Divide ratio setting bits for the prescaler

(8/9 or 16/17 for the SWIF, 64/65 or 128/129 for the SWRF)

FCIF/RF : Phase control bit for the phase detector (IF: FCIF, RF: FCRF)

LDS

: LD/fout signal select bit

NOTE: Data input with MSB first.

[Table. 1]

[Table. 4]

[Table. 5]

[Table. 6]

[Table. 7]

[Table. 8]

Table2. Binary 14-bit Programmable Reference Counter Data Setting

Divide

ratio

(R)

RRRRRRRRRRRRRR

14 13 12 11 10 9 8 7 6 5 4 3 2 1

3

00000000000011

4

00000000000100

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

16383

11111111111111

Note: Divide ratio less than 3 is prohibited.

Table.3 Test Purpose Bit Setting

T

T

1

2

LD/fout pin state

L

L

Outputs frIF

H

L

Outputs frRF

L

H

Outputs fpIF

H

H

Outputs fpRF

9

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