MAX8790 Просмотр технического описания (PDF) - Maxim Integrated

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MAX8790

Six-String White LED Driver with Active Current Balancing for LCD Panel Applications

Maxim Integrated 

MAX8790

Six-String White LED Driver with Active

Current Balancing for LCD Panel Applications

In digital dimming mode, the step-up controller and cur-

rent source are directly turned on and off by the PWM sig-

nal. The current pulse magnitude, or full-scale current, is

set by ISET and is independent of PWM duty factor. The

current-source outputs are PWM signals synchronized to

the BRT input signal (see Figure 5).

The full-scale current in both methods is specified by

resistance from the ISET pin to ground:

ILEDmax

=

20mA × 100kΩ

RISET

The acceptable resistance range is 80kΩ < RISET <

133kΩ, which corresponds to full-scale LED current of

25mA > ILEDmax > 15mA. Connect ISET to VCC for a

default full-scale LED current of 20mA. When ENA is high,

the analog dimming is enabled, when ENA is low, digital

dimming is enabled.

When the current-source output is pulse-width modulated,

current-source turn-on is synchronized with the BRT signal.

Synchronization and low jitter in the PWM signals help

reduce flicker noise in the display. The current through

each FB_ pin is controlled only during the step-up con-

verter’s on-time. During the converter’s off-time, the cur-

rent sources are turned off. The output voltage does not

discharge and stays high. Each FB_ pin can withstand 28V,

which is the pin’s maximum rated voltage.

Table 2 summarizes the characteristics of both analog

and digital dimming methods.

A PLL translates the duty cycle of the BRT input into a

reference for the MAX8790’s current sources. A resistor

from the FSET pin to ground controls the PLL’s freerunning

frequency:

f

PLL

=

10

1

× RFSET

×

800pF

The PLL’s loop filter bandwidth is set with a capacitor from

the CPLL pin to ground. This filter integrates the phase

difference between the BRT input signal and the PLL oscil-

lator. The filter bandwidth determines the PLL’s dynamic

response to frequency changes in the BRT signal. For

D = tON

tBRT

BRT

D = 50%

tON

tBRT

ILEDMAX

D = 30%

DPWM DIMMING MODE

D = 12.5%

D = 6.25%

ILED

0A

Figure 5. LED Current Control Using DPWM Dimming Mode

Table 2. Dimming Mode

MODE

ENA

Analog + DPWM > 2.1V

PLL FREQUENCY

250kΩ < RFSET < 754kΩ

CPLL

DESCRIPTION

0.1µF

Analog dimming from 100% to 12.5% brightness. From

12.5% to 1% brightness, DPWM dimming is employed.

BRT frequency range is 100Hz to 500Hz.

Direct DPWM

< 0.8V

VFSET > VCC - 0.4V, disables PLL

Direct dimming by BRT signal. BRT frequency can be

OPEN 100Hz to 2kHz; 50µs minimum BRT on-time limits the

minimum brightness.

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