Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Functional Diagrams (continued)
CS
SCLK
DIN
DSP
UPIO1
UPIO2
PU
AVDD
SERIAL
INTERFACE
CONTROL
16-BIT SHIFT
REGISTER
DVDD
AGND
DGND
MAX5581
MAX5583
MAX5585
DOUT
MUX
REGISTER
UPIO1 AND
UPIO2
LOGIC
DECODE
CONTROL
POWER-DOWN
LOGIC AND
REGISTER
INPUT
REGISTER
A
DAC
REGISTER
A
DACA
FBA
OUTA
INPUT
REGISTER
D
DAC
REGISTER
D
DACD
REF
FBD
OUTD
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