MAX3799(2009) Просмотр технического описания (PDF) - Maxim Integrated
Номер в каталоге
Компоненты Описание
производитель
MAX3799
(Rev.:2009)
(Rev.:2009)
Maxim Integrated
MAX3799 Datasheet PDF : 35 Pages
| |||
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
Typical Operating Characteristics—Limiting Amplifier (continued)
(VCC = 3.3V, TA = +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
DETERMINISTIC JITTER
vs. PULSE-WIDTH SETTING
10
PATTERN = PRBS, DATA RATE = 10.32Gbps
9
8
7
6
5
UP DOWN
4
3
EYE CROSSING
2
-7 -5 -3 -1 1 3 5 7
SET_PWCTRL[3:0]
BIAS MONITOR CURRENT
vs. TEMPERATURE
800
700
IBIAS = 12mA
600
500
400
IBIAS = 8mA
300
200
IBIAS = 2mA
100
0
-40 -25 -10 5 20 35 50 65 80 95
TEMPERATURE (°C)
PIN
1
2
3, 6, 27, 30
4
5
7
8
9
10
11
12, 15, 18,
21, 24, 25
13
Pin Description
NAME
LOS
FUNCTION
Loss-of-Signal Output, Open Drain. The default polarity of LOS is high when the level of the input
signal is below the preset threshold set by the SET_LOS DAC. Polarity of the LOS function can be
inverted by setting LOS_POL = 0. The LOS circuitry can be disabled by setting the bit LOS_EN = 0.
RSEL
VCCR
ROUT+
ROUT-
VCCD
DISABLE
SCL
SDA
Mode-Select Input, TTL/CMOS. Set the RSEL pin or RATE_SEL bit (set by the 3-wire digital interface)
to logic-high for high-bandwidth mode. Setting RSEL and RATE_SEL logic-low for high-gain mode.
The RSEL pin is internally pulled down by a 75k resistor to ground.
Power Supply. Provides supply voltage to the receiver block.
Noninverted Receive Data Output, CML. Back-terminated for 50 load.
Inverted Receive Data Output, CML. Back-terminated for 50 load.
Power Supply. Provides supply voltage for the digital block.
Transmitter Disable Input, TTL/CMOS. Set to logic-low for normal operation. Logic-high or open
disables both the modulation and bias current. Internally pulled up by an 8k resistor to VCC.
Serial-Clock Input, TTL/CMOS. This pin has a 75k internal pulldown.
Serial-Data Bidirectional Input, TTL/CMOS. Open-drain output. This pin has a 75k internal pullup,
but it requires an external 4.7k pullup resistor to meet the 3-wire digital timing specification. (Data
line collision protection is implemented.)
CSEL
Chip-Select Input, TTL/CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low
ends the cycle and resets the control state machine. Internally pulled down by a 75k resistor to
ground.
VCCT
TIN+
Power Supply. Provides supply voltage to the transmitter block.
Noninverted Transmit Data Input, CML
______________________________________________________________________________________ 13
Share Link: