MAX3675 Просмотр технического описания (PDF) - Maxim Integrated

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MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier

Maxim Integrated 

622Mbps, Low-Power, 3.3V Clock-Recovery

and Data-Retiming IC with Limiting Amplifier

±100nA. To set the threshold voltage externally (i.e., via

a DAC control), completely disable the op amp by

grounding the inverting terminal (INV). VTH then be-

comes high impedance and must be driven externally.

The comparator is configured with an active-high LOP

output. An on-chip, 6kΩ pull-up resistor is provided to

reduce external part count.

Setting the Loop Filter

The loop filter within the PLL consists of a transconduc-

tance amplifier and external filter elements RF and CF

(Figure 2). The closed-loop bandwidth of a PLL is

approximated by:

KD KO Gm RF

where KD is the gain of the phase detector, KO is the

gain of the VCO, and Gm is the transconductance of

the filter amplifier. For the MAX3675, an estimated value

of KDKOGm is 7k.

MAX3675

F(S)

GM

FIL+

CF

RF

FIL-

Because the PLL is a second-order system, a zero in

the open-loop gain is required for stability. This zero is

set by the following equation:

( ) ωz = 1 / RFCF

where the recommended external value of CF is 2.2µF.

Increasing the value of RF increases the PLL bandwidth

(fLOOP). Increasing this bandwidth improves jitter toler-

ance and jitter-generation performance, but also

reduces jitter-transfer performance. (Decreasing the

bandwidth has the opposite effect.)

This type of PLL is a classical second-order system.

Therefore, as fz (the frequency of the zero) approaches

fLOOP, the jitter-transfer peaking increases. For an over-

damped system (fz/fLOOP) < 0.25, the jitter peaking of a

second-order system can be approximated by:

Mp = 1 - (fz / fLOOP)

where Mp is the magnitude of the peaking. For

(fz/fLOOP) < 0.1, this equation holds to within 10%.

CF can be made smaller if meeting the jitter-transfer

specifications is not a requirement. For example, setting

RF to 300Ω and CF to 3.3nF increases the loop band-

width to approximately 2.2MHz (Figure 3). Loop stability

is ensured by maintaining a separation of 10x between

fLOOP and fz. Be careful when changing the value of RF.

Lower values of RF are limited by the internal resistance

of the IC, and upper values are limited by the internal

high-frequency pole.

The MAX3675 is optimally designed to acquire lock and

to provide a bit-error rate (BER) of less than 10-10 for long

strings of consecutive zeros and ones. Using the recom-

mended external component values of RF = 52.3Ω ±1%

[ ] ( ) F(s) =

Gm





s

ωz



+ 1

s CF s/ωP + 1

ωz

=1

RFCF

RF = 52.3Ω

CF = 2.2µF

ωP = internal higher - order pole

Figure 2. Loop Filter

HIGHER-

ORDER

>10x

POLE

fZ = 161kHz

CF = 3.3nF

fLOOP = 2.2MHz

RF = 300Ω

fZ = 1.38kHz

CF = 2.2µF

fLOOP = 375kHz

RF = 52.3Ω

fLOOP = KSKOGmRF

100

1k

10k

100k

1M

10M 100M

1G

FREQUENCY (Hz)

Figure 3. Loop-Filter Response

_______________________________________________________________________________________ 9

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