MAX3670EGJ Просмотр технического описания (PDF) - Maxim Integrated
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MAX3670EGJ Datasheet PDF : 12 Pages
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Low-Jitter 155MHz/622MHz
Clock Generator
PIN
1
2
3, 9, 15
4
5
6
7
8
10
11
12
13
14
16
17
18
19, 22
20
21
23
24
25
26
27
28
29
30
31
32
—
Pin Description
NAME
C2+
C2-
VCCD
TH AD J
CTH
GSEL1
GSEL2
GSEL3
LOL
GND
RSEL
REFCLK
REFCLK-
VSEL
POUT-
POUT+
VCCO
MOUT-
MOUT+
VCOIN-
VCOIN+
VC
POLAR
PSEL1
PSEL2
VCCA
COMP
OPAMP-
OPAMP+
EP
FUNCTION
Positive Filter Input. External capacitor connected between C2+ and C2- used for setting the higher-
order pole frequency (see Setting the Higher-Order Poles).
Negative Filter Input. External capacitor connected between C2+ and C2- used for setting the higher-
order pole frequency (see Setting the Higher-Order Poles).
Positive Digital Supply Voltage
Threshold Adjust Input. Used to adjust the Loss-of-Lock threshold (see LOL Setup).
Threshold Capacitor Input. A capacitor connected between CTH and ground used to control the Loss-
of-Lock conditions (see LOL Setup).
Gain Select 1 Input. Three-level pin used to set the phase-detector gain (KPD) and the frequency-
divider ratio (N2) (see Table 3).
Gain Select 2 Input. Three-level pin used to set the phase-detector gain (KPD) and the frequency-
divider ratio (N2) (see Table 3).
Gain Select 3 Input. Three-level pin used to set the phase-detector gain (KPD) and the frequency-
divider ratio (N2) (see Table 3).
Loss-of-Lock. LOL signals a TTL low when the reference frequency differs from the VCO frequency.
LOL signals a TTL high when the reference frequency equals the VCO frequency.
Supply Ground
Reference Clock Select Input. Three-level pin used to set the predivider ratio (N3) for the input
reference clock (see Table 1).
Positive Reference Clock Input
Negative Reference Clock Input
VCO Clock Select Input. Three-level pin used to set the predivider ratio (N1) for the input VCO clock
(see Table 2).
Negative Optional Clock Output, PECL
Positive Optional Clock Output, PECL
Positive Supply Voltage for PECL Outputs
Negative Main Clock Output, PECL
Positive Main Clock Output, PECL
Negative VCO Clock Input
Positive VCO Clock Input
Control Voltage Output. The voltage output from the op amp that controls the VCO.
Polarity Control Input. Polarity control of op amp input. POLAR = GND for VCOs with positive gain
transfer. POLAR = VCC for VCOs with negative gain transfer.
Optional Clock Select 1 Input. Used to set the divider ratio for the optional clock output (see Table 4).
Optional Clock Select 2 Input. Used to set the divider ratio for the optional clock output (see Table 4).
Positive Analog Supply Voltage for the Charge Pump and Op Amp
Compensation Control Input. Op amp compensation reference control input. COMP = GND for VCOs
whose control pin is VCC referenced. COMP = VCC for VCOs whose control pin is GND referenced.
Negative Op Amp Input (POLAR = 0), Positive Op Amp Input (POLAR = 1)
Positive Op Amp Input (POLAR = 0), Negative Op Amp Input (POLAR = 1)
Exposed Pad. The exposed pad must be soldered to the circuit board ground plane for proper thermal
and electrical performance.
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