MAX2837 Просмотр технического описания (PDF) - Maxim Integrated

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MAX2837

2.3GHz to 2.7GHz Wireless Broadband RF Transceiver

Maxim Integrated 

MAX2837

2.3GHz to 2.7GHz Wireless

Broadband RF Transceiver

Pin Description

PIN

NAME

FUNCTION

1

VCCRXLNA LNA Supply Voltage. Bypass with a capacitor as close as possible to the pin.

2

GNDRXLNA LNA Ground

3

B5

Receiver and Transmitter Gain-Control Logic Input Bit 5

4

RXRF+ LNA Differential Inputs. Inputs are internally DC-coupled. An external shunt inductor and series

5

RXRF- capacitors match the inputs to 100Ω differential.

6

B4

Receiver and Transmitter Gain-Control Logic Input Bit 4

7

VCCTXPAD Supply Voltage for Power-Amplifier Driver. Bypass with a capacitor as close as possible to the pin.

8

B3

Receiver and Transmitter Gain-Control Logic Input Bit 3

9

B2

Receiver and Transmitter Gain-Control Logic Input Bit 2

10

TXRF+ Power-Amplifier Driver Differential Output. PA driver output is internally matched to a 100I differential.

11

TXRF- The pins have internal DC-blocking capacitors.

12

B1

Receiver and Transmitter Gain-Control Logic Input Bit 1

13

VCCTXMX Transmitter Upconverter Supply Voltage. Bypass with a capacitor as close as possible to the pin.

14

PABIAS Transmit PA Bias DAC Output

15

SCLK Serial-Clock Logic Input of 4-Wire Serial Interface (See Figure 1)

16

CLOCKOUT Reference Clock Buffer Output

17

XTAL2 Crystal or Reference Clock Input. AC-couple a crystal or a reference clock to this analog input.

18

XTAL1

Connection for Crystal-Oscillator Off-Chip Capacitors. When using an external reference clock input,

leave XTAL1 unconnected.

19

VCCXTAL Crystal-Oscillator Supply Voltage. Bypass with a capacitor as close as possible to the pin.

20

VCCDIG Digital Circuit Supply Voltage. Bypass with a capacitor as close as possible to the pin.

21

VCCCP PLL Charge-Pump Supply Voltage. Bypass with a capacitor as close as possible to the pin.

22

GNDCP Charge-Pump Circuit Ground

23

CPOUT+ Differential Charge-Pump Output. Connect the frequency synthesizer’s loop filter between CPOUT+

24

CPOUT- and CPOUT-. (See the Typical Operating Circuit.)

25

ENABLE Operation Mode Logic Input. See Table 1 for operating modes.

26

GNDVCO VCO Ground

27

BYPASS

On-Chip VCO Regulator Output Bypass. Bypass with a 1µF capacitor to GND. Do not connect other

circuitry to this point.

28

VCCVCO VCO Supply Voltage. Bypass with a capacitor as close as possible to the pin.

29

DOUT Data Logic Output of 4-Wire Serial Interface (See Figure 1)

30

CS

Chip-Select Logic Input of 4-Wire Serial Interface (See Figure 1)

31

DIN

Data Logic Input of 4-Wire Serial Interface (See Figure 1)

32

RSSI RSSI or Temperature Sensor Multiplexed Analog Output

33

B7

Receiver Gain-Control Logic Input Bit 7

34

B6

Receiver and Transmitter Gain-Control Logic Input Bit 6

35

RXBBQ- Receiver Baseband Q-Channel Differential Outputs. In Tx calibration mode, these pins are the

36

RXBBQ+ LO leakage and sideband detector outputs.

37

RXBBI- Receiver Baseband I-Channel Differential Outputs. In Tx calibration mode, these pins are the

38

RXBBI+ LO leakage and sideband detector outputs.

39

VCCRXVGA Receiver VGA Supply Voltage

40

RXHP Receiver Baseband AC-Coupling Highpass Corner Frequency Control Logic Input

41

VCCRXFL Receiver Baseband Filter Supply Voltage

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