M7020R-083ZA1 Просмотр технического описания (PDF) - STMicroelectronics

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M7020R-083ZA1

32K x 68-bit Entry NETWORK SEARCH ENGINE

STMicroelectronics 

M7020R

Full Out (FULO[1:0]). FULO[1] and FULO[0] are

the same logical signal. One of these two signals

must be connected to the FULI of up to four down-

stream devices in a depth-cascaded table. Bit [0]

in the data array indicates if the entry is full (1) or

empty (0).This signal is asserted if all of the bits in

the data array are ’1s.’ Refer to Depth-Cascading

to Generate a “FULL” Signal, page 122.

Full Flag (FULL). When asserted, this signal in-

dicates that the table consisting of many depth-

cascaded devices is full.

Device Identification

Device Identification (ID[4:0]). The binary-en-

coded device ID for a depth-cascaded system

starts at 00000 and goes up to 11110. 11111 is re-

served for a special broadcast address that se-

lects all cascaded search engines in the system.

On a broadcast READ-only, the device with the

LDEV bit set to '1' responds.

Supplies

Chip Core Supply (VDD). This is equal to 1.8V.

Chip I/O Supply (VDDQ). This is equal to either

2.5 or 3.3V.

Test Access Port

Test Data In (TDI). This is the Test Access Port’s

Test Data In.

Test Clock (TCK). This is the Test Access Port’s

Test Clock.

Test Data Out (TDO). This is the Test Access

Port’s Test Data Out.

Test Mode Select (TMS). This is the Test Ac-

cess Port’s Test Mode Select.

Test Reset (TRST_L). This is the Test Access

Port’s Test Reset.

CLOCKS

The M7020R receives the CLK2X and PHS_L sig-

nals. It uses the PHS_L signal to divide CLK2X

and generate an internal clock (CLK), as shown in

Figure 9. Clocks (CLK2X and PHS_L)

Figure 9. The M7020R uses CLK2X and CLK for

internal operations.

CLK2X

P HS_L

CLK(1)

Note: Any reference to “CLK Cycles” means 1 cycle of the signal, “CLK.”

1. “CLK” is an internal signal.

AI04750

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