M68AW511A Просмотр технического описания (PDF) - STMicroelectronics

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производитель

M68AW511A

4 Mbit (512K x8) 3.0V Asynchronous SRAM

STMicroelectronics 

M68AW511A

Figure 12. Low VCC Data Retention AC Waveforms

3.6V

VCC

2.7V

VDR > 1.5V

E

DATA RETENTION MODE

tCDR

E ≥ VDR – 0.2V

tR

AI05447

Table 9. Low VCC Data Retention Characteristics

Symbol

Parameter

Test Condition

Min Typ

ICCDR (1) Supply Current (Data Retention) VCC = 1.5V, E ≥ VCC – 0.2V, f = 0 (3)

4.5

tCDR (1,2) Chip Disable to Power Down

0

tR (2) Operation Recovery Time

tAVAV

VDR (1) Supply Voltage (Data Retention)

E ≥ VCC – 0.2V, f = 0

1.5

Note: 1. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤0.2V.

2. Tested initially and after any design or process may affect these parameters. tAVAV is Read cycle time.

3. No input may exceed VCC +0.2V.

Max

9

Unit

µA

ns

ns

V

16/21

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