M58WR128EB10ZB6T Просмотр технического описания (PDF) - STMicroelectronics

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M58WR128EB10ZB6T

128 Mbit (8Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory

STMicroelectronics 

M58WR128ET, M58WR128EB

s The second bus cycle latches the Address and

the Data of the first word to be written.

s The third bus cycle latches the Address and the

Data of the second word to be written.

s The fourth bus cycle latches the Address and

the Data of the third word to be written.

s The fifth bus cycle latches the Address and the

Data of the fourth word to be written and starts

the Program/Erase Controller.

Read operations to the bank being programmed

output the Status Register content after the pro-

gramming has started.

Programming aborts if Reset goes to VIL. As data

integrity cannot be guaranteed when the program

operation is aborted, the memory locations must

be reprogrammed.

During Quadruple Word Program operations the

bank being programmed will only accept the Read

Array, Read Status Register, Read Electronic Sig-

nature and Read CFI Query command, all other

commands will be ignored.

Dual operations are not supported during Quadru-

ple Word Program operations and the command

cannot be suspended. Typical Program times are

given in Table 14, Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

See Appendix C, Figure 24, Quadruple Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Quadruple Word Program

command.

Enhanced Factory Program Command

The Enhanced Factory Program command can be

used to program large streams of data within any

one block. It greatly reduces the total program-

ming time when a large number of Words are writ-

ten to a block at any one time.

Dual operations are not supported during the En-

hanced Factory Program operation and the com-

mand cannot be suspended.

For optimum performance the Enhanced Factory

Program commands should be limited to a maxi-

mum of 10 program/erase cycles per block. If this

limit is exceeded the internal algorithm will contin-

ue to work properly but some degradation in per-

formance is possible. Typical Program times are

given in Table 14.

The Enhanced Factory Program command has

four phases: the Setup Phase, the Program Phase

to program the data to the memory, the Verify

Phase to check that the data has been correctly

programmed and reprogram if necessary and the

Exit Phase. Refer to Table 7, Enhanced Factory

Program Command and Figure 30, Enhanced

Factory Program Flowchart.

Setup Phase. The Enhanced Factory Program

command requires two Bus Write operations to ini-

tiate the command.

s The first bus cycle sets up the Enhanced

Factory Program command.

s The second bus cycle confirms the command.

The Status Register P/E.C. Bit SR7 should be

read to check that the P/E.C. is ready. After the

confirm command is issued, read operations

output the Status Register data. The read Status

Register command must not be issued as it will be

interpreted as data to program.

Program Phase. The Program Phase requires

n+1 cycles, where n is the number of Words (refer

to Table 7, Enhanced Factory Program Command

and Figure 30, Enhanced Factory Program Flow-

chart).

Three successive steps are required to issue and

execute the Program Phase of the command.

1. Use one Bus Write operation to latch the Start

Address and the first Word to be programmed.

The Status Register Bank Write Status bit SR0

should be read to check that the P/E.C. is ready

for the next Word.

2. Each subsequent Word to be programmed is

latched with a new Bus Write operation. The

address can either remain the Start Address, in

which case the P/E.C. increments the address

location or the address can be incremented in

which case the P/E.C. jumps to the new

address. If any address that is not in the same

block as the Start Address is given with data

FFFFh, the Program Phase terminates and the

Verify Phase begins. The Status Register bit

SR0 should be read between each Bus Write

cycle to check that the P/E.C. is ready for the

next Word.

3. Finally, after all Words have been programmed,

write one Bus Write operation with data FFFFh

to any address outside the block containing the

Start Address, to terminate the programming

phase. If the data is not FFFFh, the command is

ignored.

The memory is now set to enter the Verify Phase.

Verify Phase. The Verify Phase is similar to the

Program Phase in that all Words must be resent to

the memory for them to be checked against the

programmed data. The Program/Erase Controller

checks the stream of data with the data that was

programmed in the Program Phase and repro-

grams the memory location if necessary.

Three successive steps are required to execute

the Verify Phase of the command.

1. Use one Bus Write operation to latch the Start

Address and the first Word, to be verified. The

Status Register bit SR0 should be read to check

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