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M58LW064C

64 Mbit (4Mb x16, Uniform Block, Burst) 3V Supply Flash Memory

STMicroelectronics 

M58LW064C

dicates that the data is not, or will not be valid. Val-

id Data Ready in a high-impedance state indicates

that valid data is or will be available.

Unless Synchronous Burst Read has been select-

ed, Valid Data Ready is high-impedance. It may be

tied to other components with the same Valid Data

Ready signal to create a unique System Ready

signal.

The Valid Data Ready, R, output has an internal

pull-up resistor of approximately 1 MΩ powered

from VDDQ, designers should use an external pull-

up resistor of the correct value to meet the external

timing requirements for Valid Data Ready rising.

Refer to Figure 19.

Status/(Ready/Busy) (STS). The STS signal is

an open drain output that can be used to identify

the Program/Erase Controller status. It can be

configured in two modes:

s Ready/Busy - the pin is Low, VOL, during

Program and Erase operations and high

impedance when the memory is ready for any

Read, Program or Erase operation.

s Status - the pin gives a pulsing signal to indicate

the end of a Program or Block Erase operation.

After power-up or reset the STS pin is configured

in Ready/Busy mode. The pin can be configured

for Status mode using the Configure STS com-

mand.

When the Program/Erase Controller is idle, or sus-

pended, STS can float High through a pull-up re-

sistor. The use of an open-drain output allows the

STS pins from several memories to be connected

to a single pull-up resistor (a Low will indicate that

one, or more, of the memories is busy).

STS is not Low during a reset unless the reset was

applied when the Program/Erase controller was

active. Ready/Busy can rise before Reset/Power-

Down rises.

Program/Erase Enable (VPEN). The Program/

Erase Enable input, VPEN, is used to protect all

blocks, preventing Program and Erase operations

from affecting their data.

Program/Erase Enable must be kept High during

all Program/Erase Controller operations, other-

wise the operations is not guaranteed to succeed

and data may become corrupt.

VDD Supply Voltage. VDD provides the power

supply to the internal core of the memory device.

It is the main power supply for all operations

(Read, Program and Erase).

VDDQ Supply Voltage. VDDQ provides the power

supply to the I/O pins and enables all Outputs to

be powered independently from VDD. VDDQ can be

tied to VDD or can use a separate supply.

It is recommended to power-up and power-down

VDD and VDDQ together to avoid any condition that

would result in data corruption.

VSS Ground. Ground, VSS, is the reference for

the core power supply. It must be connected to the

system ground.

VSSQ Ground. VSSQ ground is the reference for

the input/output circuitry driven by VDDQ. VSSQ

must be connected to VSS.

Note: Each device in a system should have

VDD and VDDQ decoupled with a 0.1µF ceramic

capacitor close to the pin (high frequency, in-

herently low inductance capacitors should be

as close as possible to the package). See Fig-

ure 10, AC Measurement Load Circuit.

12/61

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