M36W0R5020T0, M36W0R5020B0
Figure 12. SRAM Write AC Waveforms, WS Controlled, GS High during Write
tAVAV
A0-A17
VALID
tAVWH
tE1LWH
tWHAX
E1S
E2S
WS
UBS, LBS
tAVWL
tE2HWH
tWLWH
tBLWH
GS
DQ0-DQ15
tGHDX
Note 2
tDVWH
tWHDX
INPUT VALID
Note: 1. WS, E1S, E2S and UBS,LBS must be asserted to initiate a write cycle.
2. The I/O pins are in output mode and input signals should not be applied.
3. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
4. UBS, LBS means both UBS and LBS.
AI09884
19/26